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    3.
    发明专利
    未知

    公开(公告)号：DE1424513A1

    公开(公告)日：1969-01-30

    申请号：DE1424513

    申请日：1962-08-18

    Applicant: IBM

    Inventor： ROCHESTER NATHANIEL

    IPC: G11C11/20 ,  G11C11/44

    Abstract: 1,010,188. Selective signalling. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 3, 1962 [Aug. 21, 1961], No. 29857/62. Heading G4H. [Also in Division H3] A superconductive selector switch or a repeater for increasing the number of energized channels in a branching system comprises a plurality of input circuits 511-514, Fig. 8, each consisting of two superconductive parallel paths 511C, 511D-514C, 514D, through which current may be selectively directed by a cryotron gate such as 514E, 514F in each path, one path in each parallel pair being coupled through a pattern of apertures 521A in a superconductive plate 521 to short-circuited superconductive turns 531, 541, 533, 542 inductively coupled to certain output circuit paths 551D, 552D, each output circuit 551, 552 consisting of two parallel superconductive paths 551C, 551D, 552C and 552D. When used as a switch currents must be induced in both short circuited turns associated with a single output circuit path for that path to become resistive, and since each short circuited turn has an extension 531A, 541A which forms an in-line cryotron in association with a different input superconductive path through a respective aperture the arrangement forms a group of AND gates, Fig. 7 (not shown). When the arrangement is used as a repeater, only one short circuited turn 932, 934, Fig. 11, is associated with a respective output circuit path 961D, 962D. In both the switch and repeater applications resetting is effected by causing the other parallel output path of each parallel pair to become resistive, and only single short-circuited turns are used, viz. 532, 534 in Fig. 8 and 931, 933 in Fig. 11. The reset control circuit consists of a superconductive pair of parallel paths 515C, 515D, Fig. 8, the conduction through which is controlled by cryotrons (not shown). For resetting the path 515D is made resistive, and the current through path 515C is coupled to the reset short circuited turn 532, 534 through apertures provided one for each output circuit. When resetting is effected only the output paths 551D, 552D are conductive. Subsequently the resetting signal is removed, and the input circuits are appropriately controlled so that selected output paths 551C, 552C become conductive. Each output path forms the control conductor of a cryotron such as 514E or 514F of a following stage. Application.-The switches and repeaters are used for the writing of a data bit or the reading of a superconductive memory array under the control of an address 128, Fig. 2, the arrangement being stated to provide more rapid operation as the various stages 201-207 of switches SW and repeaters REP may each have a different signal content which is passed from stage to stage as operation proceeds. The read or write instruction is applied from 126 and the data bit to be written is applied from 127, routing of the primary instruction through the various stages being controlled by the address 128. The number of outputs of a switch or repeater is denoted by the number in the interconnecting arrows. When the array is read the output is routed through superconductive OR gate stages 208-211 to a final output 199. Superconductive storage element.-One of two parallel superconductive paths S03, S04, Fig. 5, is respectively conductive when a " 1 " or a " 0" is stored, the other path being brought into the resistive state by the combination of a select signal in control conductor S23 and a " write 1 " or " write 0 " pulse in a respective control conductor S22, S32. The element is read out by applying a current to a control conductor S42. If a " 1 " is stored the combined current effect causes a gate conductor S41 in the output circuit to go resistive. If a "0" is stored the conductor S41 remains conductive. Construction of switch or repeater.-The superconductive plate 521 comprises two superconducting ground planes 586, 587, Fig. 10b, and a supporting body 588, the ground planes being used as return paths for the circuit currents. At each aperture position the adjacent short-circuited turn 512C is dipped as shown to improve the coupling with the conductor 421. Another detail of interest is the use of a return portion in each output circuit path (see Figs. 8 and 11) so that the path is coupled with the whole of the adjacent shortcircuited turn.

    4.
    发明专利
    未知

    公开(公告)号：DE1095026B

    公开(公告)日：1960-12-15

    申请号：DEI0012345

    申请日：1956-10-19

    Applicant: IBM DEUTSCHLAND

    Inventor： ROCHESTER NATHANIEL ,  JOHNSON JACOB RAYMOND ,  AMDAHL GENE MYRON ,  MUTTER WALTER EDWARD

    IPC: G06K9/46

    Abstract: 845,548. Character recognition. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 19,1956 [Oct. 20, 1955], No. 31860/56. Class 106 (1). The numerals or characters of an intelligence pattern are interpreted by sensing means detecting the presence of intersections and bounded regions in each of the entities and differentiating by the types of intersections and bounded regions therein. The scanning device need not be light and the representations may be magnetic, sonic, chemical or electrostatic. The recognition of numerals is described, using the detection of triple intersections by a central vertical line, upper and lower inlets to left and right, long vertical and black lines and the presence of lakes (Fig. 13, not shown). The area containing the numeral is scanned by a light spot bit by bit in vertical sweeps giving black or white (1, 0) responses, and a memory device stores the respective signals allowing coded signal representations of the combinations to be recorded and interpreted as the presence or absence of the various characteristics of the numerals. The provision of a Shape Rules Circuit and a memory trigger storage enables a decoder of Christmas tree shape to detect the numeral being scanned and operate the appropriate punch or output. The Shape Rules circuit modifies the coded numbers in a marking register and the shape memory triggers are turned on or the contents of the marking register modified by the logical coincidence of certain events involving the presence of white or black, the contents of the register and the state of the temporary triggers. The flow diagram, Fig. 1, shows scan, control and recognition circuits. The light spot from C.R.T. scanner 70 is reflected by the symbols on a document 74 to give a signal at photo-tubes 76 which is fed to a Black-White circuit 80 comprising anplifiers and limiters giving black and white signals at leads B, B, respectively. The line scanning is vertically upwards in thirty-two steps, only sixteen of which are used for recognition purposes, and the beam is unblanked for only a short period at each elemental area. The horizontal frame scan is from left to right and a complete absence of black in any vertical scan indicates end of character. The recognition circuits comprise shape rule circuit 96 and storage means comprising a marking register 97 and memory triggers 98, the latter storing the findings of circuits 96. The marking register has 16 storage positions, one for each area of vertical scan, each assigned an arbitrary coded number. White is coded -, black is coded 1, white following black horizontally is coded 2, black following a white coded 2 is coded 5, a white area between a lower black intercept and a middle black intercept is coded 3, and a white area between a middle black and an upper black is coded 4, Figs. 14 and 16. Coded 3 and 4 at the end of character indicate lower and upper right inlet respectively. Each coded number is fed from the shape rules circuit 96, via digit encode circuit 120 into the marking register 97. A series of coded 0's actuates the reset and endof-character circuit 132, the signal being fed to " O.K. to Punch " lead 136 and the decoder circuit 100. The character recognised proceeds to control the punch 102. The circuits of cathode followers, multi-grid switches, inverters, " And " and " 0 + " circuits, limiters, amplifiers, photo-multipliers, triggers, multivibrators, counters, peakers, core and relay drivers deflection units and core-shifting registers are described (Figs. 19-74, not shown). The document is carried on a standard electric typewriter which is stationary for a period of 32 vertical sweeps before spacing in the usual way, although in a modification the light spot sweeps vertically over a continuously-moving document. The travel of the carriage is reset by closing contacts in a relay circuit, the register counters being neutralized during this period. Only photo-multiplier signals of a certain magnitude are passed by a limiter circuit to the video circuits..The action and timing of the control circuits, i.e. marking register, reset and black white determination are described in detail in the Specification. The marking register (Fig. 30, not shown) comprises three sixteen-position shift registers made up of magnetic cores which store binary information, and each position is coded 1 or #1 so as to determine in the decoding circuits which of the coded 0-5 is appropriate for feeding to the programme rules circuit (Figs. 3F, 3G, 3H, not shown). Rule 1 circuit comprises an " OR " circuit 514 fed by a coded 0, 3 or 4 and an " AND " circuit 516 receiving the black lead B from Black White cable 388 and the output of the " OR " circuit, so that a coded 1 is fed back to the Encode circuit and the marking register, if a black signal follows a coded 0, 3 or 4. Rule 3 uses an " AND " circuit 518 to detect a white B following a coded 1 and feeds a coded 2 to the marking register. Rules 4-8 detect triple intersection, i.e. a black-whiteblack-white-black sequence, which is at least two bits wide. Primer trigger P 0 is " On " for the first black and Primer trigger P 1 is " on " if trigger P 0 is " on " and a white area is sensed. Similarly triggers P 2 , P 3 and P 4 go " On " for subsequent black and white sensings, and finally a memory trigger M 0 is in the " On " condition. Rule 9 detects the lower left inlet basic shape, requiring detection of triple intersection (M 0 is ON), and a coded 0 present in the lower of the two white areas. Connected to the input of the " AND " circuit of memory trigger M 1 are M 0 , P 0 in " On position (indicating passing of first black intercept), #P 2 in OFF position (second black not reached), an " in 0 " from Rule circuit input cable 460 and a fifth input lead #P 5 which determines that the presence of the lower inlet is detected after the detection of the triple intersection. Similarly the other memory triggers react to Rule circuits which indicate upper left inlet, lower and upper right inlet, lake basic shape, long vertical black line and the small left inlet, respectively. Other Rule circuits are utilized for the process of expanding and preventing imperfections in the numeral characters giving wrong indications, as, for example, serifs and other lines in the figures 7 and 2. As shown in Fig. 3I, the connections " M 0 "-" M 7 " from the memory triggers feed through relay drivers 574-581 to relays R 0 - R 7 controlling switches in the Christmas Tree Shape Decoder which determine which character is sensed, the O.K. to Punch signal on line 318 energizing the slow relay R 10 and line 414 to punch or print the character recognized.

    ONE-HANDED KEYBOARD AND ITS CONTROL MEANS
    7.
    发明专利
    ONE-HANDED KEYBOARD AND ITS CONTROL MEANS 未知

    公开(公告)号：CA1085487A

    公开(公告)日：1980-09-09

    申请号：CA262533

    申请日：1976-10-01

    Applicant: IBM

    Inventor： BEQUAERT FRANK C ,  ROCHESTER NATHANIEL

    IPC: G06F3/02 ,  B41J3/26 ,  B41J5/10 ,  G06F3/023 ,  H01H13/807 ,  H03M11/08 ,  H04L15/04 ,  H04L17/02

    Abstract: ONE-HANDED KEYBOARD AND ITS CONTROL MEANS A keyboard which has ten keys controlled by the four fingers and four keys controlled by the thumb of the same hand. On it, the operator forms chords somewhat as a pianist forms chords on a piano. It allows the user to type at normal speed using only one hand and offers the possibility of typing at a faster rate than the conventional two-handed keyboard. The operator presses several keys at once, as when playing a chord on a piano. Each finger or thumb can press one key, or overlap two or four adjacent keys to press the two or four keys. There are 27 such finger positions on the 10 finger keys and 7 thumb positions on the four thumb keys. The thumb position on the thumb keys select the alphabet/case, output order of characters in the chord, a space character preceding the chord, and capitalizing of the first outputted character of a chord. The finger positions on the finger keys select the characters in the alphabet/case selected by the thumb position. The disclosed system describes a mechanical design of the keys, and control circuits that interprets the chords and emits signals representing the strings of characters implied by the chords.

    8.
    发明专利
    未知

    公开(公告)号：DE1111430B

    公开(公告)日：1961-07-20

    申请号：DEI0009980

    申请日：1955-03-21

    Applicant: IBM DEUTSCHLAND

    Inventor： ROCHESTER NATHANIEL ,  BASHE CHARLES JULIAN ,  BUCHHOLZ WERNER ,  CRAGO ROBERT PAUL ,  FOX PHILIP EVERETT ,  HADDAD JERRIER ABDO ,  PHELPS BYRON EUGENE

    IPC: G06F15/78

    Abstract: 800,505. Digital electric calculating-apparatus; electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 18, 1955 [March 22, 1954], No. 7918/55. Class 106 (1). Electronic data processing apparatus includes input and output devices interconnected by a computer which employs variable length words, the lengths being demarcated by special coded characters. General. The electronic computer illustrated in Figs. 1a and 1b comprises a C.R.T. memory M, an accumulator including a C.R.T. store AS, and input/output magnetic tape units T. Words comprise a variable number of coded characters each represented by seven bits, Fig. 1c, comprising four numerical bits 1, 2, 4, 8, two zone bits A, B and a redundancy check bit C such as to make the total of " 1 "s in a character always odd. Numbers are in decimal form and have their digits represented in the excess-three code, the zone bits being "0." Words are separated by field marks " +," "-," Fig. 1c, the mark " - " being used only for numbers stored in the memory to indicate a negative sign. In the accumulator store, a negative sign is indicated by numerical " 9 " with " + " field mark zone digits. The field marks and other special characters are detected by recognition circuits CRC associated with two characters registers CR1, CR2, Fig. 1b, which receive characters as they are read out from the memory or accumulator store via main bus MB or accumulator storage bus AB, and also form a buffer between the memory and the tape units. The memory comprises 50 pairs of C.R.T.s; a pair is selected by unit selector US and a " left " or " right " C.R.T. of this pair by memory left/right control MC. The beam in the selected C.R.T. may be deflected to one of 100 character positions by memory deflection circuits MD. The circuits US, MC, MD are controlled by the portions indicated of a 4-decimal-digit address through memory switch MS. A word location is given by the address of the "right-hand " field mark (the one with the higher address number); e.g. the address of the number 123, 456, Fig. 1h, is 0037. Transfer to and from tape (writing and reading) is effected in the order of increasing address numbers (" left to right "), but transfer between the memory and the accumulator is effected in the reverse order (" right to left "). The accumulator store AS, which normally stores one word only, comprises a single C.R.T. having 100 character positions selected by deflection circuits ASD controlled by 2-digit addresses through switch ASS, addresses normally being selected in ascending order. A separate computer cycle is provided for dealing with each character, timing control signals being obtained from clock C and waveform generator WG. An instruction word, e.g. the word at address 0008, Fig. 1h, always comprises 6 characters, viz., an operation-defining character, an " address " portion (4 characters or digits) and a field mark, and is read out from the memory in ascending address order (operation character first). The addresses are sequentially set up in a programme counter PC (in a 1, 2, 2, 4 code) during the 6 successive character cycles of " instruction time," the computer being controlled by instruction timer IT to pass the operation character to interpreter II and the address digits via memory address translator MAT to a register MAR operating in the 1, 2, 2, 4 code. At the commencement of the subsequent " execution time," in which a timer ET is selected to carry out the instruction, the address in register MAR is transferred to counter MAC and normally applied via code ambiguity eliminator MAE to the switch MS to select a required memory location, and the amount registered on a two-decimal-digit starting point counter SPC may be transposed to an accumulator storage address counter AAC and applied via ambiguity eliminator ASAE to switch ASS to select an accumulator location when required. During subsequent execution character cycles, the count in MAC may be stepped down and the count in AAC stepped up to select successive character positions in the memory and accumulator store. Words from M and AS may be sent character by character to the comparator adder time/complement circuits CATC to perform arithmetic and other operations. The flow of information is controlled by routing circuits R. During a portion of each character cycle a regeneration counter RC is effective systematically to regenerate all the stored bits in the C.R.T.s, 50 tubes (one in each pair) being regenerated simultaneously in the main memory M. In some instructions, the memory is not used, and the " address " number in MAC is employed, e.g. to determine how the word stored in AS is to be modified, or to select, through in/out unit selector IOS, one of the tape or other input/ output units. The character emitter CE emits timed pulses representing certain numeral and other characters. The electronic circuits consist primarily of Eccles-Jordan double triode trigger circuits (T), coincidence switches (S) which usually produce a negative output in response to two positive inputs, diode AND and OR circuits, inverters (I) and cathode followers (CF); circuit diagrams for these components are given in the Specification. The computer is described below under the following headings: (1) Clock and waveform generator; timing signal rotation. (2) Basic counter. (3) Ambiguity eliminator. (4) Input/Output. (5) Character Registers and Character Recognition Circuits. (6) Memory address translator and register. (7) Memory address counter and ambiguity eliminator. (8) Programme counter. (9) Regeneration counter. (10) Memory and associated selection circuits. (11) Accumulator storage and associated circuits. (12) Memory and accumulator sign circuits. (13) Comparator, adder, true complement and associated circuits. (14) Adder and complementer. (15) Instruction timer; sequence of events during instruction time. (16) Instruction interpreter. (17) Routing circuits. (18) Execution timers; instructions. (19) Add or subtract instruction. (20) Reset add and subtract instructions. (21) Add to memory instruction. (22) Compare instruction. (23) Multiplication. (24) Division. (25) Instructions involving accumulator, store but not memory, rounding off; positioning decimal point. (26) " Store "-instruction. (27) Transfer of control instructions. (28) Tape instructions. (1) Clock and waveform generator; timing signal notation. The clock C, Fig. 1b, comprises a 1 mc/s. oscillator and a pulse distributing circuit similar to that of Specification 750,259 for defining regeneration (G), and read (R) and write (W) periods in a character cycle. The computer may be held in the " G " portion of the cycle under control of a " repeat regeneration" signal. The clock controls waveform generator circuits WG which develop timing signals such as those shown in Figs. 2c and 2i. Signals are denoted by the number of microseconds their leading edges occur after an index time G0-W7 and by their duration (D); e.g. the pulse L202, Fig. 2i, would be denoted WO1 (D2) meaning a pulse starting 1 Ás. after W0 and lasting 2 Ás. A train of pulses may also be denoted; e.g. R22 (D1)4 indicates 4 pulses each of 1 Ás. duration and starting 2 Ás. after R2 and succeeding index times (L203, Fig. 21). An inverted or complementary signal is indicated by c; e.g. L124c is a positive pulse coinciding with L124, Fig. 2c. (2) Basic counter. A decimal counting circuit CT1, Fig. 1d, comprises four double-triode triggers 101, 102, 103, 104 having weighted values 1, 2 (called 2C), 2, 4 respectively. The triggers may be reset to the " off " or " O " condition (right triode conducting) by a positive pulse at 11, inverted in 131 and applied through diodes 133-136 to the right anodes. Trigger 101 responds to negative input pulses at 15 and, for every second pulse, supplies a negative output pulse to diodes 105 and 107 connected respectively via line 107a to the right-hand input only of trigger 102 and via diode 110 and line 112 to both inputs of 103. Thus, after the second input pulse, trigger 102 is switched " on " and applies a positive gating potential via resistor 108 to diode 107 to allow subsequent pulses from 101 to switch trigger 103. Triggers 101, 103, 104 then operate in normal binary fashion until trigger 104 is switched back to " O " in response to the tenth input pulse, when the negative pulse from its right anode is applied via diode 116 to carry output terminal 27, and to line 118 to reset trigger 102. A value may be entered also in parallel, during a " dumping " operation, by selectively applying "1"-representing negative pulses to terminals 16-19. The registered value may be changed to its 9's complement by a negative pulse applied via 13 to line 126 to switch all the - triggers to the opposite condition, the connections between the triggers being inhibited by applying a positive signal at 12 to inverter 121 so as to drive line 122 negative. Output terminals 21-26 enable the registered value to be read out. After the complementing, and possibly after parallel entry, the representation of any value between 2 and 7 will be different from that obtained during normal stepping of the counter. This alternative representation is translated into the normal one in an ambiguity eliminator (described below). A simplified counter CT2 (Fig. 1e, not shown) having no provision for complementing, also is employed. (3) Ambiguity eliminator. The circuit AE, Fig. 1f, is a code interpreting circuit which receives respectively from terminals 21, 23-26 of a counter such as CT1, Fig. 1d, a negative input at 16 when the " 1 " trigger is " on," positive inputs at 17, 18 when the " 2 " triggers (102 and 103 respectively) are " on," and a positive input at 19 or 20 according to whether the "4" trigger is " off " or " on," and supplies positive outputs selectively to 21-24, corresponding to the weighted values 1, 2G, 2, 4, to represen

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