公开(公告)号：JPH11312734A

公开(公告)日：1999-11-09

申请号：JP3969299

申请日：1999-02-18

Applicant: IBM

Inventor： EDWARD C CORNEY III ,  STEPHEN E LUCY ,  COTE WILLIAM J ,  RONALD D GOLDBLATT

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/283 ,  H01L21/98 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a forming method of a contact to a copper metal inside an insulating layer via on a semiconductor wafer. SOLUTION: This contact forming method includes the five steps comprising a first step of forming a wafer 20 having a patterned copper layer 22, a second step of forming an insulating film 24 on the copper layer 22, a third step of forming a via 26 in the insulating film 24, a fourth step of forming a wafer 20 in reducing atmosphere for reducing a copper oxide on the copper in the via 26, to produce a copper as well as the fifth step of bringing the wafer 20 into contact with the copper inside the via 26, without exposing the wafer 20 to the oxidizing environment but to make a liner 52 adhere to the wafer 20. In such a constitution, this contact forming method can solve the problem of copper bounce detected in the via 26 cleaned up by conventional sputtering process. In addition, the liner 52 is selected for the adhesion and the avoidance of copper diffusion as well.

公开(公告)号：JP2004214626A

公开(公告)日：2004-07-29

申请号：JP2003396313

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WILLIAM F LANDERS ,  SHAW THOMAS M ,  LLERA-HURLBURT DIANA ,  CROWDER SCOTT W ,  MCGAHAY VINCENT J ,  MALHOTRA SANDRA G ,  DAVIS CHARLES R ,  RONALD D GOLDBLATT ,  ENGEL BRETT H

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04

CPC classification number: H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To obtain improved crack stopping and contaminant barriers for an IC chip. SOLUTION: On-chip overlapped crack end barrier structure is constituted. A conductive material in barrier structure design is used for forming the depth of several conductive layers, by wiring each barrier to a contact pad and a device pin and connecting a monitoring device to a chip. Upper surface deposit, consisting of a material such as polyimide, suppresses peeling off of layers. Other barriers may include structural characteristics for completely shielding moisture absorption and oxidation, as compared with typical crack stopping structure. Thereto, other barriers are constituted so as to give crack stop protection, to be electrically connected to a monitoring device and so as to test the capacitance/resistance of the barrier structure to show the complete states of the barriers to a user. A barrier destroyed by cracks or humidity absorption/oxidation shows deviation in the capacitance/resistance. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：MY134071A

公开(公告)日：2007-11-30

申请号：MYPI20020376

申请日：2002-02-05

Applicant: IBM

Inventor： GEORGE F WALKER ,  RONALD D GOLDBLATT ,  PETER A GRUBER ,  RAYMOND R HORTON ,  KEVIN S PETRARCA ,  RICHARD P VOLANT ,  TIEN-JEN CHENG

IPC: H01L23/48 ,  H01L21/3205 ,  H01L23/52 ,  H01L21/60 ,  H01L23/485

Abstract: A PROCESS IS DESCRIBED FOR FORMING A COMMON INPUT-OUTPUT (I/O) SITE THAT IS SUITABLE FOR BOTH WIRE-BOND AND SOLDER BUMP FLIP CHIP CONNECTIONS, SUCH AS CONTROLLED-COLLAPSE CHIP CONNECTIONS (C4).THE PRESENT INVENTION IS PARTICULARLY SUITED TO SEMICONDUCTOR CHIPS THAT USE COPPER AS THE INTERCONNECTION MATERIAL, IN WHICH THE SOFT DIELECTRICS USED IN MANUFACTURING SUCH CHIPS ARE SUSCEPTIBLE TO DAMAGE DUE TO BONDING FORCES. THE PRESENT INVENTION REDUCES THE RISK OF DAMAGE BY PROVIDING SITE HAVING A NOBLE METAL (26) ON THE TOP SURFACE OF THE PAD, WHILE PROVIDING A DIFFUSION BARRIER (22) TO MAINTAIN THE HIGH CONDUCTIVITY OF THE METAL INTERCONNECTS. PROCESS STEPS FOR FORMING AN I/O SITE WITHIN A SUBSTRATE (20) ARE REDUCED BY PROVIDING A METHOD FOR SELECTIVELY DEPOSITING METAL LAYERS IN A FEATURE (21) FORMED IN THE SUBSTRATE. SINCE THE I/O SITES OF THE PRESENT INVENTION MAY BE USED FOR EITHER WIRE-BOND OR SOLDER BUMP CONNECTIONS, THIS PROVIDES INCREASED FLEXIBILITY FOR CHIP INTERCONNECTION OPTIONS, WHILE ALSO REDUCING PROCESS COSTS.(FIG 2D)