公开(公告)号：JP2000029684A

公开(公告)日：2000-01-28

申请号：JP11475699

申请日：1999-04-22

Applicant: IBM

Inventor： MARK A CHECK ,  RONALD M SMITH ,  JOHN S RIPTY ,  ERIK M SCHWARZ ,  TIMOTHY J SLEEGAL ,  CHARLES F WEBB

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To support a high-frequency operation by arranging the extension of an operation code outside the starting four bytes of an instruction format and assigning a code so that a machine can determine the accurate format of an instruction with only starting light bits of the code. SOLUTION: As for a base register 18, a multiplexer selector 19 directly controls a base multiplexer 20 and selects and sends a default base position to a CPR register file 15. A 2nd base register is gated from an instruction text to a B prime slot in the base register 18 in a 1st cycle and the multiplexer selector 19 is set to 1. A critical path, therefore, reaches a register for an address adder 16 from the base register 18 through the multiplexer 20 controlled by the selector 19 and the GPR register file 15. Thus, combination logic is excluded from the critical path.

公开(公告)号：JP2000029685A

公开(公告)日：2000-01-28

申请号：JP11477199

申请日：1999-04-22

Applicant: IBM

Inventor： MARK A CHECK ,  RONALD M SMITH ,  JOHN S RIPTY ,  ERIK M SCHWARZ ,  TIMOTHY J SLEEGAL ,  CHARLES F WEBB

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To enable a foating-point processor to determine the accurate format of an instruction by determining that an instruction is in 2nd format by decoding an operation code and gating information needed for address generation to an adder according to the decision result. SOLUTION: A 2nd base register is gated from an instruction text to a B prime slot in a base register 18 in a 1st cycle and a multiplexer selector 19 is set to 1. A critical path, therefore, reaches a register for an address adder 16 from the base register 18 through a multiplexer 20 controlled by the selector 19 and a GPR file 15. In this case, the floating-point processor decodes a 1st part of the operation code to determine that the instruction is in 2nd format, and gates information needed for address generation to the adder 16 according to the determination result.