公开(公告)号：EP2394304A4

公开(公告)日：2014-05-21

申请号：EP10739003

申请日：2010-02-02

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY ,  SLEIGHT JEFFREY W

IPC: H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02667 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696 ,  Y10S977/762

公开(公告)号：WO2005055290A3

公开(公告)日：2005-09-09

申请号：PCT/EP2004053204

申请日：2004-12-01

Applicant: IBM ,  IBM UK ,  BEDELL STEPHEN ,  COHEN GUY ,  CHEN HUAJIE

Inventor： BEDELL STEPHEN ,  COHEN GUY ,  CHEN HUAJIE

IPC: H01L21/20 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/324

Abstract: A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate in which the strained semiconductor is a thin semiconductor layer having a thickness of less than 50 nm that is located directly atop an insulator layer of a preformed silicon-on-insulator substrate is provided. Wafer bonding is not employed in forming the SSOI substrate of the present invention.

Abstract translation: 一种制造应变半导体绝缘体（SSOI）衬底的方法，其中应变半导体是厚度小于50nm的薄半导体层，其直接位于预成型的绝缘体上硅衬底上的绝缘体层的顶部 被提供。 在形成本发明的SSOI基板时不使用晶片接合。

公开(公告)号：WO2005043614A3

公开(公告)日：2005-11-03

申请号：PCT/EP2004052704

申请日：2004-10-28

Applicant: IBM ,  IBM UK ,  CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

Inventor： CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

IPC: H01L21/762 ,  H01L27/12 ,  H01L27/144 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L27/14

CPC classification number: H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

Abstract translation: 提供了用于制造绝缘体上锗（GOI）衬底材料的方法，通过该方法制造的GOI衬底材料以及可以包括至少本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶上的掩埋绝缘体层以及位于掩埋绝缘体层顶上的含Ge层，优选纯Ge。 在本发明的GOI基板材料中，含Ge层也可以被称为GOI膜。 GOI膜是其中可以形成器件的本发明衬底材料的层。

公开(公告)号：EP2801105A4

公开(公告)日：2014-12-03

申请号：EP12864109

申请日：2012-12-13

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY ,  MAJUMDAR AMLAN ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

公开(公告)号：JP2003109918A

公开(公告)日：2003-04-11

申请号：JP2001300046

申请日：2001-09-28

Applicant: IBM

Inventor： CANAPERI DONALD F ,  COHEN GUY ,  RYAN HAN ,  OTT JOHN A ,  LOFARO MICHAEL ,  CHU JACK O

IPC: B24B37/00 ,  C08J5/14 ,  C09K3/14 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To provide a method and device by which a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool can be incorporated. SOLUTION: CMP is performed with a descending force of 1 psi, backward air pressure of 0.5 psi, platen speed of 50 rpm, carrier speed of 30 rpm, and slurry flow rate of 140 milliliter.

公开(公告)号：JP2002016255A

公开(公告)日：2002-01-18

申请号：JP2001143342

申请日：2001-05-14

Applicant: IBM

Inventor： COHEN GUY ,  WONG HON-SUM PHILIP

IPC: H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a double-gate integrated circuit and its structure. SOLUTION: The method includes a step for forming a laminated structure, having a channel layer and first insulation layers provided on the respective side surface of the channel layer, a step for forming an opening in the laminated structure, a step for forming source and drain regions in the opening, a step for removing a portion of the laminated structure for leaving a first portion of the channel layer exposed to the external, a step for forming a first gate dielectric layer in the channel layer, a step for forming a first gate electrode in the first gate dielectric layer, a step for removing a portion of the laminated structure to leave a second portion of the channel layer exposed to the external, a step for forming a second gate dielectric layer in the channel layer, a step for forming a second gate electrode in the second gate dielectric layer, and a step for doping the source and drain regions through self-aligned ion implantation. In this case, the first and second gate electrodes are formed independently of each other.

公开(公告)号：JP2008072107A

公开(公告)日：2008-03-27

申请号：JP2007223096

申请日：2007-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COHEN GUY ,  CHU JACK OON ,  OTT JOHN ALBRECHT ,  ROOKS MICHAEL J ,  SOLOMON PAUL

IPC: H01L29/786 ,  H01L29/06

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a field effect transistor (FET) with a channel formed by a semiconductor nanowire (semiconductor nanowire channel) and doped semiconductor source and drain regions. SOLUTION: A FET structure with a semiconductor nanowire forming the FET channel and doped source and drain regions formed by radial epitaxy from the semiconductor nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有由半导体纳米线（半导体纳米线通道）和掺杂的半导体源极和漏极区域形成的沟道的场效应晶体管（FET）。 解决方案：公开了一种具有形成FET沟道的半导体纳米线和由半导体纳米线体径向外延形成的掺杂源极和漏极区的FET结构。 讨论了顶盖门控和底部门控纳米线FET结构。 源极和漏极制造可以使用选择性或非选择性外延。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：GB2503847B

公开(公告)日：2015-07-01

申请号：GB201318578

申请日：2012-03-05

Applicant: IBM

Inventor： COHEN GUY ,  DIMITRAKOPOULOS CHRISTOS ,  GRILL ALFRED

IPC: H01L29/786 ,  H01L29/775

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

公开(公告)号：GB2494947B

公开(公告)日：2014-11-19

申请号：GB201208378

申请日：2011-03-31

Applicant: IBM

Inventor： SLEIGHT JEFFREY ,  BANGSARUNTIP SARUNYA ,  COHEN GUY

IPC: H01L29/04 ,  H01L29/06 ,  H01L29/786

公开(公告)号：GB2487316B

公开(公告)日：2014-07-23

申请号：GB201203673

申请日：2010-09-21

Applicant: IBM

Inventor： COHEN GUY ,  FRANK DAVID JAMES

IPC: B81B3/00

Abstract: A nonvolatile nano-electromechanical system device is provided and includes a cantilever structure, including a beam having an initial shape, which is supported at one end thereof by a supporting base and a beam deflector, including a phase change material (PCM), disposed on a portion of the beam in a non-slip condition with a material of the beam, the PCM taking one of an amorphous phase or a crystalline phase and deflecting the beam from the initial shape when taking the crystalline phase.