-
公开(公告)号：DE2504288A1
公开(公告)日：1975-09-11
申请号：DE2504288
申请日：1975-02-01
Applicant: IBM
Inventor： HAIMS MURRAY J , HAO HSIEH TUNG , LEBIZAY GERALD , WEISS ALFRED
Abstract: 1466366 Parallel binary adders INTERNATIONAL BUSINESS MACHINES CORP 5 Feb 1975 [7 March 1974] 4874/75 Heading G4A A parallel binary adder comprises registers 30, 31 which initially respectively store an augend A and an addend B, the quantitites A, B being gated 33, 34 to an exclusive-OR circuit 32 where the quantity A#B is generated and stored (overwriting A) in register 30 via a gate 35, the quantities A#B and B then being gated 37, 38 to a carry generation circuit 36 which generates a carry C therefrom, the quantities A#B and C then being gated 33, 39 to the exclusive-OR circuit 32 which generates the sum S = (A#B)# C therefrom and stores the sum S in register 30. The carry generation circuit 36 may be implemented in AND/OR/NOT logic (Fig. 1, not shown) and operates using Boolean algorithms given in the Specification to simultaneously generate two carries C k-1 , C k from a lower order carry C k+1 . In a second embodiment of the carry generation circuit 36, Fig. 2 (not shown), NOR logic functionally equivalent to Fig. 1 is used to facilitate its implementation as a LSI circuit, the inverses C k-1 , C k of the carries being simultaneously generated from the lower order carry C k+1 .
-
公开(公告)号：DE69025464D1
公开(公告)日：1996-03-28
申请号：DE69025464
申请日：1990-12-14
Applicant: IBM
Inventor： BLAUM MIGUEL MARIO , HAO HSIEH TUNG
-
Patent Agency Ranking
公开(公告)号：DE3485929T2
公开(公告)日：1993-04-01
申请号：DE3485929
申请日：1984-05-30
Applicant: IBM
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , HAO HSIEH TUNG , MARKSTEIN PETER WILLY , RADIN GEORGE
Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.
-
公开(公告)号：DE3481560D1
公开(公告)日：1990-04-12
申请号：DE3481560
申请日：1984-05-30
Applicant: IBM
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , HAO HSIEH TUNG , MARKSTEIN PETER WILLY , RADIN GEORGE
Abstract: @ A mechanism for performing a run-time storage ad-dress validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry (52) for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.
-
公开(公告)号：DE69025464T2
公开(公告)日：1996-09-19
申请号：DE69025464
申请日：1990-12-14
Applicant: IBM
Inventor： BLAUM MIGUEL MARIO , HAO HSIEH TUNG
-
公开(公告)号：DE3485929D1
公开(公告)日：1992-10-29
申请号：DE3485929
申请日：1984-05-30
Applicant: IBM
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , HAO HSIEH TUNG , MARKSTEIN PETER WILLY , RADIN GEORGE
Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.
-
公开(公告)号：DE3481233D1
公开(公告)日：1990-03-08
申请号：DE3481233
申请日：1984-02-29
Applicant: IBM
Inventor： HAO HSIEH TUNG , LING HUEI , SACHAR HOWARD EDWARD , WEISS JEFFREY , YAMOUR YANNIS JOHN
Abstract: A pair of inherently sequential instructions, having an instruction dependency of the type in which the subsequent instruction requires as an input operand the result of the earlier instruction execution, can nevertheless be simultaneously executed by two data flow facilities (primary and secondary) under control of a control unit, without the requirement that both data flow facilities be fully equipped for all instructions. … The secondary data flow facility of this invention is generally less massive and less sophisticated than the primary data flow facility but is more sophisticated in a critical organ, the adder. The adder in the secondary data flow facility has one additional operand capability. The three-input adder of the secondary data flow facility thus is capable of replicating internally a result of the two-input adder of the primary data flow facility. Using this replicated primary adder "result", together with the additional operand capability, the secondary data flow facility three- input adder executes the dependent subsequent instruction of the pair simultaneously with the earlier instruction execution by the primary data flow facility.
-
-
-
-
-
-
Search Results
7
records
(took 0.016 seconds)
