公开(公告)号：DE69017198D1

公开(公告)日：1995-03-30

申请号：DE69017198

申请日：1990-05-15

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  SAINT GEORGES ERIC ,  ORSATTI DANIEL ,  TOUBOL GILLES ,  VERPLANKEN FABRICE ,  NICOLAS FRANCOIS

IPC: H04Q3/52 ,  H04L12/64

Abstract: The hybrid packet and circuit switching system allows to merge the packet and circuit traffics from user interface modules 2-1 to 2-N on TDM bus 4-1 to 4N and to transfer packet information from one module to another module or exchange circuit information between modules. The circuit exchange or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. There is a routing indication which is common to the packet and circuit bursts for controlling the switching of the bursts by the switch 1, which is performed by piggy backing the target module address for the circuit bursts as well as for the packet burst with the data bursts. The marking tables which are needed for the circuit burst allocation are located in the user interface modules.

公开(公告)号：DE69017198T2

公开(公告)日：1995-08-17

申请号：DE69017198

申请日：1990-05-15

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  SAINT GEORGES ERIC ,  ORSATTI DANIEL ,  TOUBOL GILLES ,  VERPLANKEN FABRICE ,  NICOLAS FRANCOIS

IPC: H04Q3/52 ,  H04L12/64

Abstract: The hybrid packet and circuit switching system allows to merge the packet and circuit traffics from user interface modules 2-1 to 2-N on TDM bus 4-1 to 4N and to transfer packet information from one module to another module or exchange circuit information between modules. The circuit exchange or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. There is a routing indication which is common to the packet and circuit bursts for controlling the switching of the bursts by the switch 1, which is performed by piggy backing the target module address for the circuit bursts as well as for the packet burst with the data bursts. The marking tables which are needed for the circuit burst allocation are located in the user interface modules.