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    METHOD AND DEVICE FOR TRANSMITTING AND RECEIVING PACKET
    2.
    发明专利
    METHOD AND DEVICE FOR TRANSMITTING AND RECEIVING PACKET 失效

    公开(公告)号：JPH1051472A

    公开(公告)日：1998-02-20

    申请号：JP12519797

    申请日：1997-05-15

    Applicant: IBM

    Inventor： CALVIGNAC JEAN ,  ORSATTI DANIEL ,  VERPLANKEN FABRICE

    IPC: H04Q3/00 ,  H04L12/28

    Abstract: PROBLEM TO BE SOLVED: To reserve irreducible bandwidth when connection is established and perform transmission and reception, and improve the efficiency of a network by scheduling received packets at a packet network node under control over an absolute time according to a speed corresponding to the reserved bandwidth. SOLUTION: A dedicated minimum service connection is expected with a queue 101 specified by a search mechanism 100, the connection queue is scheduled by a shaper unit 111 according to the speed corresponding to the reserved bandwidth by controlling the absolute time 190, and a queue identifier is stored. Then the identifier is read out and the starting packet of the corresponding queue is transmitted. While there is a free cell space, a priority mechanism function 178 performs ready identifier queue resetting out of a queue group 174, also preforms queue resetting from a minimum service connection queue 15 corresponding to the identifier, and fills a cell space 170 with ready cells.

    3.
    发明专利
    未知

    公开(公告)号：DE69022025D1

    公开(公告)日：1995-10-05

    申请号：DE69022025

    申请日：1990-03-13

    Applicant: IBM

    Inventor： BARUCCHI GERARD ,  GALCERA JOSE ,  TOUBOL GILLES ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

    IPC: G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

    Abstract: The synchronization circuit resynchronizes the data bits received from remote devices from line or link 20-1 with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in a n-bit cyclic buffer (114-1) with the received bit clock CS and they are sequentially picked at the opposite buffer position with the central clock CO The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

    4.
    发明专利
    未知

    公开(公告)号：DE68916413D1

    公开(公告)日：1994-07-28

    申请号：DE68916413

    申请日：1989-03-14

    Applicant: IBM

    Inventor： BARUCCHI GERARD ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

    IPC: G06F15/16 ,  G06F15/167 ,  G06F15/173

    Abstract: The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.

    6.
    发明专利
    未知

    公开(公告)号：DE69017198D1

    公开(公告)日：1995-03-30

    申请号：DE69017198

    申请日：1990-05-15

    Applicant: IBM

    Inventor： CALVIGNAC JEAN ,  SAINT GEORGES ERIC ,  ORSATTI DANIEL ,  TOUBOL GILLES ,  VERPLANKEN FABRICE ,  NICOLAS FRANCOIS

    IPC: H04Q3/52 ,  H04L12/64

    Abstract: The hybrid packet and circuit switching system allows to merge the packet and circuit traffics from user interface modules 2-1 to 2-N on TDM bus 4-1 to 4N and to transfer packet information from one module to another module or exchange circuit information between modules. The circuit exchange or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. There is a routing indication which is common to the packet and circuit bursts for controlling the switching of the bursts by the switch 1, which is performed by piggy backing the target module address for the circuit bursts as well as for the packet burst with the data bursts. The marking tables which are needed for the circuit burst allocation are located in the user interface modules.

    7.
    发明专利
    未知

    公开(公告)号：DE69017198T2

    公开(公告)日：1995-08-17

    申请号：DE69017198

    申请日：1990-05-15

    Applicant: IBM

    Inventor： CALVIGNAC JEAN ,  SAINT GEORGES ERIC ,  ORSATTI DANIEL ,  TOUBOL GILLES ,  VERPLANKEN FABRICE ,  NICOLAS FRANCOIS

    IPC: H04Q3/52 ,  H04L12/64

    Abstract: The hybrid packet and circuit switching system allows to merge the packet and circuit traffics from user interface modules 2-1 to 2-N on TDM bus 4-1 to 4N and to transfer packet information from one module to another module or exchange circuit information between modules. The circuit exchange or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. There is a routing indication which is common to the packet and circuit bursts for controlling the switching of the bursts by the switch 1, which is performed by piggy backing the target module address for the circuit bursts as well as for the packet burst with the data bursts. The marking tables which are needed for the circuit burst allocation are located in the user interface modules.

    9.
    发明专利
    未知

    公开(公告)号：DE69022025T2

    公开(公告)日：1996-04-18

    申请号：DE69022025

    申请日：1990-03-13

    Applicant: IBM

    Inventor： BARUCCHI GERARD ,  GALCERA JOSE ,  TOUBOL GILLES ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

    IPC: G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

    Abstract: The synchronization circuit resynchronizes the data bits received from remote devices from line or link 20-1 with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in a n-bit cyclic buffer (114-1) with the received bit clock CS and they are sequentially picked at the opposite buffer position with the central clock CO The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

    10.
    发明专利
    未知

    公开(公告)号：DE68916413T2

    公开(公告)日：1995-01-26

    申请号：DE68916413

    申请日：1989-03-14

    Applicant: IBM

    Inventor： BARUCCHI GERARD ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

    IPC: G06F15/16 ,  G06F15/167 ,  G06F15/173

    Abstract: The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.

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