公开(公告)号：JPH11345168A

公开(公告)日：1999-12-14

申请号：JP9647799

申请日：1999-04-02

Applicant: IBM

Inventor： SAN HOO ZON ,  JOEL ABRAHAM SILVERMAN

IPC: G06F12/08 ,  G06F12/10

Abstract: PROBLEM TO BE SOLVED: To provide a method for accessing a cache memory in a data processing system. SOLUTION: This cache memory is provided with a transformation index buffer 33, together with a memory array 31 and a directory. The cache memory can be accessed by an effective address containing a byte field, row field and effective page number field. In order to facilitate a cache access process, a transformation array 34 having the same number of rows as the transformation index buffer 33 is provided. The respective rows of the transformation array 34 have as many array items as the product of a row number per page of a system memory and the set associativity of a cache. The transformation array 34 is updated after the contents of the directory or transformation index buffer 33 have been updated. In order to decide whether or not the cache memory stores data related to the translated address, the transformation array can be accessed corresponding to the contents of the row field at the effective address.

公开(公告)号：JPH11353177A

公开(公告)日：1999-12-24

申请号：JP11974499

申请日：1999-04-27

Applicant: IBM

Inventor： SAN HOO ZON ,  HAAM PETER HOFSTY ,  KEVIN JOHN NOFUKA ,  JOEL ABRAHAM SILVERMAN

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To use the register set in a processor more efficiently by mapping sources and target architecture registers in instructions to one group of physical registers and generating a list of tags corresponding to physical registers which are not used here. SOLUTION: One given instruction is loaded to one execution unit and the list of tags corresponding to specific registers which are not used is generated. All the items in a table A for the physical registers are linked on logical OR basis to generate a vector for accurately discriminating which register is used by an instruction being executed. This vector is passed to a structure B which generates the tag of a physical register possibly assigned as a target to a following target although it is not used. The vector structure B generates a bit indicating the adequacy of the generated tag as well. The generated tag becomes ineffective only when the number of usable physical registers is insufficient.