公开(公告)号：JP2004200684A

公开(公告)日：2004-07-15

申请号：JP2003413888

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN SHYNG-TSONG ,  DALTON TIMOTHY J ,  DAVIS KENNETH M ,  HU CHAO-KUN ,  JAMIN FEN F ,  KALDOR STEFFEN K ,  KRISHNAN MAHADEVAIYER ,  KUMAR KAUSHIK ,  MICHAEL F ROFARO ,  SANDRA G MARUHOTORA

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide the structure of an integrated circuit having a logic/functional device layer and an interconnection layer above it. SOLUTION: This interconnection layer has a substrate, a conductive feature 122 in the substrate, and a cap 151 which is formed only above the conductive feature. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2000208499A

公开(公告)日：2000-07-28

申请号：JP37251599

申请日：1999-12-28

Applicant: IBM

Inventor： MICHAEL AAMAKOSUTO ,  SANDRA G MARUHOTORA ,  TINA WAGNER ,  RICHARD WISE

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/336 ,  H01L21/60 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an improved self-aligned spacer. SOLUTION: A conductive gate structure is provided on a semiconductor substrate 1 and a first dielectric gate cap material layer and a second dielectric material layer 5 are provided thereon. Subsequently, a region 6 of high dopant level is provided on the second dielectric material layer 5 for fabricating a self-aligned spacer. Selective etching takes place through the dopant and a self-aligned conductive spacer is defined.