公开(公告)号：JP2006019724A

公开(公告)日：2006-01-19

申请号：JP2005182361

申请日：2005-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHINTHAKINDI ANIL K ,  SCHNURMANN HENRI D

IPC: H01G5/04 ,  B81C1/00 ,  H01G5/01 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06

CPC classification number: H01G5/18 ,  H01G5/38

Abstract: PROBLEM TO BE SOLVED: To provide a micro-electromechanical system (MEMS) variable capacitor where movable comb type drive electrodes with opposite polarities are simultaneously manufactured on the same substrate, which operate independently. SOLUTION: These electrodes are formed as an interdigital structure so as to maximize electrical capacitance. To assure that a varactor does not fail as the result of stress that possibly separates a dielectric material from a conductive element, this MEMS variable capacitor contains a CMOS manufacturing step combined with an elastomeric material selectively used in a region where stress is maximum. Combining this CMOS process and a conductive elastomeric material between vias increases an overall sidewall region, thus increasing electrical capacitance density. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种微机电系统（MEMS）可变电容器，其中具有相反极性的可动梳状驱动电极同时制造在独立工作的相同基板上。

解决方案：这些电极形成为叉指结构，以使电容最大化。 为了确保变容二极管不会由于可能将介电材料与导电元件分离的应力的结果而失败，该MEMS可变电容器包含与在应力最大的区域中选择性地使用的弹性体材料组合的CMOS制造步骤。 将该CMOS工艺与导电弹性体材料结合在通孔之间增加了整个侧壁区域，从而增加了电容密度。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：BR8702439A

公开(公告)日：1988-02-23

申请号：BR8702439

申请日：1987-05-13

Applicant: IBM

Inventor： JACOBS SCOTT L ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI D ,  ZINGHER ARTHUR R

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H01L23/30

Abstract: An integrated circuit chip packaging structure, preferably having a semiconductor base substrate (1), i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers (8) being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connect the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each have coplanar ground, power (39, 40) and signal lines (19, 20), with at least one power (16) or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed, low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.

公开(公告)号：CA1277434C

公开(公告)日：1990-12-04

申请号：CA534157

申请日：1987-04-08

Applicant: IBM

Inventor： JACOBS SCOTT L ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI D ,  ZINGHER ARTHUR R

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538

Abstract: MODULE FOR PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT CHIPS ON A BASE SUBSTRATE An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connect the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each have coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed; low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.