公开(公告)号：BR8702439A

公开(公告)日：1988-02-23

申请号：BR8702439

申请日：1987-05-13

Applicant: IBM

Inventor： JACOBS SCOTT L ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI D ,  ZINGHER ARTHUR R

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H01L23/30

Abstract: An integrated circuit chip packaging structure, preferably having a semiconductor base substrate (1), i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers (8) being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connect the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each have coplanar ground, power (39, 40) and signal lines (19, 20), with at least one power (16) or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed, low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.

公开(公告)号：CA1277434C

公开(公告)日：1990-12-04

申请号：CA534157

申请日：1987-04-08

Applicant: IBM

Inventor： JACOBS SCOTT L ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI D ,  ZINGHER ARTHUR R

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538

Abstract: MODULE FOR PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT CHIPS ON A BASE SUBSTRATE An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connect the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each have coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed; low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.

公开(公告)号：DE3781370T2

公开(公告)日：1993-04-01

申请号：DE3781370

申请日：1987-05-05

Applicant: IBM

Inventor： JACOBS SCOTT LAURENCE ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI DANIEL

IPC: H01L23/52 ,  H01L23/538 ,  H01L27/00

Abstract: A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer (9) having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments (32) to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure (9) of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures (9) are combined by decals (29, 31) to form a central processing unit (1) of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments (32).

公开(公告)号：DE3781370D1

公开(公告)日：1992-10-01

申请号：DE3781370

申请日：1987-05-05

Applicant: IBM

Inventor： JACOBS SCOTT LAURENCE ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI DANIEL

IPC: H01L23/52 ,  H01L23/538 ,  H01L27/00

Abstract: A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer (9) having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments (32) to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure (9) of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures (9) are combined by decals (29, 31) to form a central processing unit (1) of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments (32).