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    LOW-TEMPERATURE REFLOW DIELECTRIC BPSG FLUORIDE
    1.
    发明专利
    LOW-TEMPERATURE REFLOW DIELECTRIC BPSG FLUORIDE 失效

    公开(公告)号：JPH11288930A

    公开(公告)日：1999-10-19

    申请号：JP1271499

    申请日：1999-01-21

    Applicant: IBM ,  SIEMENS AG ,  LAM RES CORP

    Inventor： KIRCHHOF MARKUS ,  CHAKRAVARTI ASHIMA ,  ILG MATTHIAS ,  MCKINLEY KEVIN A ,  NGUYEN SON V ,  SHAPIRO MICHAEL J

    IPC: H01L21/31 ,  C23C16/40 ,  H01L21/316

    Abstract: PROBLEM TO BE SOLVED: To improve gap-filling characteristics by performing the reaction and adhesion of an F-BPSG layer under specific ranges of pressure and temperature by the mixture of a reduced pressure chemical vapor growth process and the reactants of TEOS and FTES. SOLUTION: Orthotetraethyl silicate(TEOS), fluoroalkoxysilane(FTES) containing fluorine, boron and phosphor dopants, and an oxygen supply source are mixed with each another for reaction at a temperature of approximately 650-850 deg., under a pressure of approximately 0.5-5 torr in a chamber. Then, a fluorine dope BPSG layer (borophospho-silicate-glass) 22 that is generated by a reaction is allowed to adhere onto a semiconductor substrate 11 which is arranged in the chamber. Then, a layered semiconductor element is subjected to reflow at a temperature that is lower than approximately 800 deg.C, thus flattening the adhering layer and as a result filling the opening of a wafer 10 with a large aspect ratio and a small gap with the same adhesion/annealing temperature and the same dopant concentration of boron and phosphor.

    Method, program and system for reconstructing dynamic processor for low power without reducing performance based on workload execution characteristic
    4.
    发明专利
    Method, program and system for reconstructing dynamic processor for low power without reducing performance based on workload execution characteristic 有权
    基于工作载荷执行特性降低性能的低功耗动态处理器的方法，程序和系统

    公开(公告)号：JP2009151778A

    公开(公告)日：2009-07-09

    申请号：JP2008316674

    申请日：2008-12-12

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： LOUIS BENNY CAPS JR ,  BELL JR ROBERT H ,  SHAPIRO MICHAEL J

    IPC: G06F9/38 ,  G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D50/20

    Abstract: PROBLEM TO BE SOLVED: To provide a method, a system and a program for dynamically reconstructing a pipeline type processor so as to operate by reduced power consumption without reducing existing performance. SOLUTION: When an individual unit or stage in a processor executes a given workload, by monitoring or detecting these performances, the respective stages uses a high performance circuit up to time when reduction is detected in throughput performance, and at that time, the stages are reconstituted so as to use a low performance circuit to be adjusted to the reduced performance throughput requirements of using less power. A power loss is optimized by constituting so as to retreat the processor to low performance design from high performance design to be adjusted to guarantee of a detected performance characteristic of an execution workload. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于动态重建流水线型处理器以便降低功耗而不降低现有性能的方法，系统和程序。 解决方案：当处理器中的单个单元或者阶段执行给定的工作负载时，通过监视或检测这些性能，各个阶段在吞吐量性能中检测到减少时，使用高性能电路， 这些阶段被重构，以便使用低性能电路来调整以降低使用较少功率的性能吞吐量要求。 通过构成功率损耗来优化，以便将处理器从高性能设计撤回到低性能设计以进行调整，以保证检测到的执行工作负载的性能特征。 版权所有（C）2009，JPO＆INPIT

    Method for giving sharing cache line in multiprocessor data processing system, computer readable medium and multiprocessor data processing system
    5.
    发明专利
    Method for giving sharing cache line in multiprocessor data processing system, computer readable medium and multiprocessor data processing system 有权
    在多处理器数据处理系统中提供共享高速缓存行的方法，计算机可读介质和多处理器数据处理系统

    公开(公告)号：JP2009134716A

    公开(公告)日：2009-06-18

    申请号：JP2008290605

    申请日：2008-11-13

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BELL JR ROBERT H ,  COOK THOMAS EDWARD ,  NAYAR NARESH ,  LUIS BENNY CAPPS JR ,  SHAPIRO MICHAEL J

    IPC: G06F12/08

    CPC classification number: G06F12/0817 ,  Y02D10/13

    Abstract: PROBLEM TO BE SOLVED: To provide a directory-based coherency method, system and program for giving a requested cache line from a plurality of candidate memory sources in a multiprocessor system based on a sensed temperature value or power consumption value at each memory source. SOLUTION: By providing a temperature or power consumption sensor in each of the memory sources (e.g., in a core, cache memory, memory controller, etc.) that share a requested cache line, a control logical unit uses a signal from the temperature or power consumption sensors to determine which memory source should give the requested cache line by giving the signal which directs to provide the cache line to a requester, only to the memory source which involves allowed power consumption. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种基于目录的一致性方法，系统和程序，用于基于在每个存储器处的感测温度值或功耗值，在多处理器系统中从多个候选存储器源提供所请求的高速缓存行 资源。 解决方案：通过在共享所请求的高速缓存线的每个存储器源（例如，在核心，高速缓冲存储器，存储器控制器等中）提供温度或功率消耗传感器，控制逻辑单元使用来自 温度或功率消耗传感器，以确定哪个存储器源应该通过给出指示将请求者提供高速缓存行的信号提供给所请求的高速缓存行，而仅涉及涉及允许的功耗的存储器源。 版权所有（C）2009，JPO＆INPIT

    Integrierter Entkopplungskondensator, bei welchem leitfähige Durchkontaktierungen durch das Substrat verwendet werden
    6.
    发明专利
    Integrierter Entkopplungskondensator, bei welchem leitfähige Durchkontaktierungen durch das Substrat verwendet werden 未知

    公开(公告)号：DE112010004326T5

    公开(公告)日：2012-08-23

    申请号：DE112010004326

    申请日：2010-11-09

    Applicant: IBM

    Inventor： MCALLISTER MICHAEL F ,  SHAPIRO MICHAEL J ,  KIM TAE HONG ,  SPROGIS EDMUND J

    IPC: H01L27/08 ,  H01L23/522 ,  H01L25/04

    Abstract: Bei einem Kondensator (180) in einem Halbleitersubstrat (10) wird eine leitfähige Durchkontaktierung durch das Substrat (Through-Substrate Via, TSV) (80) als eine innere Elektrode und eine säulenförmige dotierte Halbleiterzone als eine äußere Elektrode verwendet. Der Kondensator (80) stellt eine große Entkopplungskapazität auf einer kleinen Fläche bereit und beeinflusst nicht die Schaltungsdichte oder einen 3DSi-Strukturentwurf. In dem Halbleitersubstrat (10) können weitere leitfähige TSVs bereitgestellt sein, um für eine elektrische Verbindung für Stromversorgungen und eine Signalübertragung durch dieses hindurch zu sorgen. Der Kondensator (180) weist eine niedrigere Induktivität als ein herkömmliches Kondensatorfeld mit vergleichbarer Kapazität auf, wodurch in dem Stromversorgungssystem gestapelter Halbleiterchips eine Verringerung des Hochfrequenzrauschens ermöglicht wird.

    7.
    发明专利
    未知

    公开(公告)号：DE69832035T2

    公开(公告)日：2006-07-13

    申请号：DE69832035

    申请日：1998-12-07

    Applicant: LAM RES CORP ,  IBM ,  SIEMENS AG

    Inventor： KIRCHHOF MARKUS ,  CHAKRAVARTI ASHIMA ,  ILG MATTHIAS ,  MCKINLEY KEVIN A ,  NGUYEN SON V ,  SHAPIRO MICHAEL J

    IPC: C23C16/40 ,  H01L21/31 ,  C23C16/44 ,  H01L21/316

    Abstract: An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. Preferably the glass deposition is performed at a temperature of about 750-850 DEG C and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.

    8.
    发明专利
    未知

    公开(公告)号：DE69832035D1

    公开(公告)日：2005-12-01

    申请号：DE69832035

    申请日：1998-12-07

    Applicant: LAM RES CORP ,  IBM ,  SIEMENS AG

    Inventor： KIRCHHOF MARKUS ,  CHAKRAVARTI ASHIMA ,  ILG MATTHIAS ,  MCKINLEY KEVIN A ,  NGUYEN SON V ,  SHAPIRO MICHAEL J

    IPC: H01L21/31 ,  C23C16/40 ,  H01L21/316 ,  C23C16/44

    Abstract: An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. Preferably the glass deposition is performed at a temperature of about 750-850 DEG C and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.

    Integrated decoupling capacitor employing conductive through-substrate vias
    10.
    发明专利
    Integrated decoupling capacitor employing conductive through-substrate vias 未知

    公开(公告)号：GB2488078A

    公开(公告)日：2012-08-15

    申请号：GB201209593

    申请日：2010-11-09

    Applicant: IBM

    Inventor： MCALLISTER MICHAEL ,  SHAPIRO MICHAEL J ,  KIM TAE HONG ,  SPROGIS EDMUND J

    IPC: H01L21/822 ,  H01L21/768 ,  H01L23/522 ,  H01L23/64 ,  H01L27/06

    Abstract: A capacitor (180) in a semiconductor substrate (10) employs a conductive through-substrate via (TSV) (80) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor (80) provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSVs can be provided in the semiconductor substrate (10) to provide electrical connection for power supplies and signal transmission therethrough. The capacitor (180) has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

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