公开(公告)号：EP1979932A4

公开(公告)日：2012-03-14

申请号：EP07710130

申请日：2007-01-15

Applicant: IBM

Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

IPC: H01L21/77 ,  H01L21/302 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2250669A4

公开(公告)日：2012-07-25

申请号：EP09710899

申请日：2009-02-11

Applicant: IBM

Inventor： LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  STEIN KENNETH J

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和由环形导体层包围的塞子层。 一种用于制造穿通基底通孔的方法，包括在基底内形成盲孔，并且在盲孔内依次形成并随后在盲孔内进行平坦化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：JP2005142562A

公开(公告)日：2005-06-02

申请号：JP2004319023

申请日：2004-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： PAUL S ANDREE ,  CASEY JON A ,  HORTON RAYMOND R ,  PATEL CHIRAQ S ,  SPROGIS EDMUND J ,  SUNDLOF BRIAN R

IPC: H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L21/76 ,  H01L23/14 ,  H01L25/04 ,  H01L25/18 ,  H05K3/34

CPC classification number: H01L21/486 ,  H01L23/147 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for filling a via within a wafer, particularly, for filling a blind via first, and various devices for carrying out the method. SOLUTION: The method includes a step for evacuating the via of air, a step for trapping at least a portion of a wafer and a paste with which to fill the via between two surfaces, and a step for filling the via by applying pressure to the paste. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于在晶片内填充通孔的方法，特别是用于首先填充盲孔，以及用于执行该方法的各种装置。 解决方案：该方法包括用于抽空空气通道的步骤，用于捕获至少一部分晶片和用于填充两个表面之间的通孔的浆料的步骤，以及通过施加填充通孔的步骤 对浆糊的压力。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003249622A

公开(公告)日：2003-09-05

申请号：JP2003019022

申请日：2003-01-28

Applicant: IBM

Inventor： LASKY JEROME B ,  NOWAK EDWARD J ,  SPROGIS EDMUND J

IPC: H01L25/18 ,  H01L21/768 ,  H01L23/48 ,  H01L23/50 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To provide chip-on-chip module and a forming method belonging to the same. SOLUTION: A first semiconductor chip is connected to a second semiconductor chip. The first chip comprises a first wiring layer and a first conductive substrate in the first side and the second side of the first chip, respectively. A power supply voltage VDD is adapted so as to be electrically connected to the second side of the first chip. The second chip comprises a second wiring layer and a second conductive substrate in the first side and the second side of the second chip, respectively. A grounding voltage GND is adapted so as to be electrically connected to the second side of the second chip. The first side of the first chip is connected to the first side of the second chip. The power supply voltage VDD and the grounding voltage GND are adapted so as to supply an electric power to the first and the second chips. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2006196894A

公开(公告)日：2006-07-27

申请号：JP2006001619

申请日：2006-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HOOK TERENCE B ,  RASSEL ROBERT M ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  MURPHY WILLIAM J

IPC: H01L23/36 ,  H01L23/373

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a resistor that has a heat sink with excellent heat conduction. SOLUTION: This heat sink includes a conduction path that has a high-thermal conductivity metal and other thermal conductors. In order that an electrical resistor may not be short-circuited to earth by this thermal resistor, a thin layer with a high-thermal conductivity electric insulator is interposed between the thermal conductor and the resistor's body. Accordingly, since heat is conducted to the heat sink in a direction in which the thermal conductor with high thermal conductivity moves away from the resistor, the resistor can pass a large amount of current. In addition to the fact that a parasitic capacitance and other electric parasitic actions that help reduce high-frequency responses from the electric resistor are lowered, various structures of a thermal conductor and heat sink are achieved through which favorable thermal conduction characteristics are obtained. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有散热器的具有优异热传导性的电阻器。 解决方案：该散热器包括具有高导热性金属和其他热导体的导电路径。 为了使该电阻器不会被该热电阻器短路到地，具有高导热电绝缘体的薄层插入在热导体和电阻体之间。 因此，由于在热导率高的导体从电阻器移开的方向向散热器传导热量，所以电阻器能够通过大量的电流。 除了有助于降低来自电阻器的高频响应的寄生电容和其他电寄生作用降低之外，还实现了热导体和散热器的各种结构，从而获得了良好的热传导特性。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2013066455A3

公开(公告)日：2014-05-08

申请号：PCT/US2012049414

申请日：2012-08-03

Applicant: IBM ,  COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETHANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETHANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L23/4825 ,  H01L21/6835 ,  H01L21/76819 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L29/1054 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/73251 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/804 ,  H01L2224/80487 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.

Abstract translation: 用于粘合基板表面，粘合基板组件以及用于键合衬底组件的设计结构的方法。 使用器件衬底（10）的第一表面（15）形成产品芯片（25）的器件结构（18,19,20,21）。 在产品芯片上形成用于器件结构的互连结构的布线层（26）。 布线层被平坦化。 临时处理晶片（52）可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面（54）被结合到最终的手柄基板（56）。 然后将临时手柄晶片从组件中取出。

公开(公告)号：WO2011090852A2

公开(公告)日：2011-07-28

申请号：PCT/US2011020913

申请日：2011-01-12

Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

Abstract translation: 制造集成电路结构的方法在衬底（100;图1）中形成第一开口并用保护性衬垫排列第一开口。 （102）该方法将材料沉积到第一开口（104）中并且在衬底上形成保护材料。 保护材料包括过程控制标记并且包括在第一开口上方并与第一开口对齐的第二开口。 （108）该方法通过保护材料中的第二开口从第一开口移除材料。 （110）过程控制标记包括保护材料内的凹部，其仅部分地延伸穿过保护材料，使得过程控制标记下方的部分基板不受移除材料的过程的影响。

公开(公告)号：WO2011057238A3

公开(公告)日：2011-08-18

申请号：PCT/US2010055949

申请日：2010-11-09

Applicant: IBM ,  MCALLISTER MICHAEL F ,  SHAPIRO MICHAEL J ,  KIM TAE HONG ,  SPROGIS EDMUND J

Inventor： MCALLISTER MICHAEL F ,  SHAPIRO MICHAEL J ,  KIM TAE HONG ,  SPROGIS EDMUND J

IPC: H01L27/02 ,  H01L21/70

CPC classification number: H01L28/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A capacitor (180) in a semiconductor substrate (10) employs a conductive through-substrate via (TSV) (80) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor (80) provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSVs can be provided in the semiconductor substrate (10) to provide electrical connection for power supplies and signal transmission therethrough. The capacitor (180) has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

Abstract translation: 半导体衬底（10）中的电容器（180）采用导电贯穿衬底通孔（TSV）（80）作为内部电极和柱状掺杂半导体区域作为外部电极。 电容器（80）在小面积上提供大的去耦电容，并且不影响电路密度或Si3D结构设计。 可以在半导体衬底（10）中提供附加的导电TSV，以提供用于电源和通过其的信号传输的电连接。 电容器（180）具有比具有相当电容的传统电容器阵列的电感更低的电感，从而能够降低层叠半导体芯片的电源系统中的高频噪声。

公开(公告)号：WO2007084879A3

公开(公告)日：2008-02-21

申请号：PCT/US2007060544

申请日：2007-01-15

Applicant: IBM ,  ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

IPC: H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/44 ,  H01L21/77

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).

Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一介电层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述电介质隔离（250）的周边内并且在所述绝缘隔离（250）的周边内并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至小于衬底厚度（001）的深度（D1）。 填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平面化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。

公开(公告)号：JP2005175483A

公开(公告)日：2005-06-30

申请号：JP2004353571

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COLGAN EVAN G ,  FEGER CLAUDIS ,  GOTH GARY F ,  KATOPIS GEORGE A ,  MAGERLEIN JOHN H ,  SPROGIS EDMUND J

IPC: H01L23/34 ,  H01L21/50 ,  H01L21/56 ,  H01L23/10 ,  H01L23/12 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/367 ,  H01L23/3737 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To reduce the temperature of a hot spot of a chip by locally reducing the layer thickness of a compliant thermally conductive material on the chip.
SOLUTION: In an integrated circuit package structure within MCM or SCM, a compliant thermally conductive material is applied between a heat-producing integrated circuit and a substrate attached thereto. A thinner layer of the compliant thermally conductive material is arranged between the chip and the substrate in this region after assembling, and as a result, a raised region aligned to a high power density region higher than the average on the active front surface of the chip is defined at the backside of the chip so that the temperature of the "hot spot" on the chip is reduced. In an exemplary embodiment, the substrate comprises one of a heat sink, cooling plate, heat spreader, heat pipe, heat hat, package lid, and other cooling members.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过局部减小芯片上柔性导热材料的层厚来降低芯片热点的温度。 解决方案：在MCM或SCM中的集成电路封装结构中，将柔性导热材料施加在发热集成电路和附着于其之间的衬底之间。 柔性导热材料的较薄层在组装之后在该区域中布置在芯片和基板之间，结果是与高于芯片的有源前表面上的平均值的高功率密度区域对准的凸起区域 被限定在芯片的背面，使得芯片上的“热点”的温度降低。 在示例性实施例中，基板包括散热器，冷却板，散热器，热管，加热帽，封装盖和其它冷却构件中的一个。 版权所有（C）2005，JPO＆NCIPI