公开(公告)号：WO2012145097A2

公开(公告)日：2012-10-26

申请号：PCT/US2012028987

申请日：2012-03-14

Applicant: IBM ,  ERICKSON KARL R ,  PAONE PHIL C ,  PAULSEN DAVID P ,  SHEETS JOHN E ,  UHLMANN GREGORY J ,  WILLIAMS KELLY L

Inventor： ERICKSON KARL R ,  PAONE PHIL C ,  PAULSEN DAVID P ,  SHEETS JOHN E ,  UHLMANN GREGORY J ,  WILLIAMS KELLY L

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/12

CPC classification number: H01L21/2652 ,  H01L21/76267 ,  H01L29/1087

Abstract: A semiconductor chip (100) has an independently voltage controlled silicon region (110) that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors (140) and threshold voltages of field effect transistors (130) overlying the independently voltage controlled silicon region (110). A bottom, or floor, of the independently voltage controlled silicon region (110) is a deep implant (105) of opposite doping to a doping of a substrate of the independently voltage controlled silicon region (110). A top, or ceiling, of the independently voltage controlled silicon region (110) is a buried oxide (103) implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation (106). Voltage of the independently voltage controlled silicon region (110) is applied through a contact structure (107) formed through the buried oxide (103).

Abstract translation: 半导体芯片（100）具有独立电压控制的硅​​区域（110），其是用于控制eDRAM沟槽电容器（140）的电容器值和覆盖独立电压控制硅区域（130）的场效应晶体管（130）的阈值电压的电路元件 （110）。 独立电压控制的硅​​区域（110）的底部或底面是与独立电压控制的硅​​区域（110）的衬底的掺杂相反的掺杂的深注入（105）。 独立电压控制的硅​​区域（110）的顶部或顶部是衬底中的掩埋氧化物（103）注入。 独立电压控制的硅​​区域的侧面是深沟槽隔离（106）。 独立电压控制的硅​​区域（110）的电压通过穿过掩埋氧化物（103）形成的接触结构（107）施加。

公开(公告)号：GB2502480B

公开(公告)日：2014-04-30

申请号：GB201315408

申请日：2012-03-14

Applicant: IBM

Inventor： ERICKSON KARL R ,  PAONE PHIL C ,  PAULSEN DAVID ,  SHEETS JOHN E ,  UHLMANN GREGORY J ,  WILLIAMS KELLY L

IPC: H01L27/108

Abstract: A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

公开(公告)号：DE112012001195T5

公开(公告)日：2013-12-12

申请号：DE112012001195

申请日：2012-03-14

Applicant: IBM

Inventor： ERICKSON KARL R ,  SHEETS JOHN E ,  UHLMANN GREGORY J ,  PAONE PHIL C ,  PAULSEN DAVID P ,  WILLIAMS KELLY L

IPC: H01L27/12 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108

Abstract: Ein Halbleiterchip (100) weist eine unabhängig spannungsgesteuerte Siliciumzone (110) auf, welche ein Schaltungselement ist, das zum Steuern von Kondensatorwerten von eDRAM-Grabenkondensatoren (140) und Schwellenspannungen von Feldeffekttransistoren (130) geeignet ist, welche über der unabhängig spannungsgesteuerten Siliciumzone (110) liegen. Ein unterer Teil oder Boden der unabhängig spannungsgesteuerten Siliciumzone (110) ist eine tiefe Implantation (105) entgegengesetzter Dotierung, bezogen auf eine Dotierung eines Substrats der unabhängig spannungsgesteuerten Siliciumzone (110). Ein oberer Teil oder eine Decke der unabhängig spannungsgesteuerten Siliciumzone (110) ist eine Implantation eines vergrabenen Oxids (103) in dem Substrat. Seiten der unabhängig spannungsgesteuerten Siliciumzone sind eine Tiefgrabenisolierung (106). Die Spannung der unabhängig spannungsgesteuerten Siliciumzone (110) wird durch eine Kontaktstruktur (107) angelegt, die durch das vergrabene Oxid (103) hindurch ausgebildet ist.

公开(公告)号：GB2502480A

公开(公告)日：2013-11-27

申请号：GB201315408

申请日：2012-03-14

Applicant: IBM

Inventor： ERICKSON KARL R ,  PAONE PHIL C ,  PAULSEN DAVID ,  SHEETS JOHN E ,  UHLMANN GREGORY J ,  WILLIAMS KELLY L

IPC: H01L27/108

Abstract: A semiconductor chip (100) has an independently voltage controlled silicon region (110) that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors (140) and threshold voltages of field effect transistors (130) overlying the independently voltage controlled silicon region (110). A bottom, or floor, of the independently voltage controlled silicon region (110) is a deep implant (105) of opposite doping to a doping of a substrate of the independently voltage controlled silicon region (110). A top, or ceiling, of the independently voltage controlled silicon region (110) is a buried oxide (103) implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation (106). Voltage of the independently voltage controlled silicon region (110) is applied through a contact structure (107) formed through the buried oxide (103).