公开(公告)号：GB2562945A

公开(公告)日：2018-11-28

申请号：GB201812599

申请日：2016-11-22

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：GB2560866A

公开(公告)日：2018-09-26

申请号：GB201812607

申请日：2017-01-06

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：GB2562948A

公开(公告)日：2018-11-28

申请号：GB201812854

申请日：2017-01-06

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：GB2562945B

公开(公告)日：2020-08-12

申请号：GB201812599

申请日：2016-11-22

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：GB2562948B

公开(公告)日：2019-06-19

申请号：GB201812854

申请日：2017-01-06

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.