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    Formation of self-aligned bottom spacer for vertical transistors
    1.
    发明专利
    Formation of self-aligned bottom spacer for vertical transistors 未知

    公开(公告)号：GB2581116B

    公开(公告)日：2021-03-03

    申请号：GB202008885

    申请日：2018-12-14

    Applicant: IBM

    Inventor： CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

    IPC: H01L29/78 ,  H01L21/336

    Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

    Field effect transistor stack with tunable work function
    2.
    发明专利
    Field effect transistor stack with tunable work function 未知

    公开(公告)号：GB2562945A

    公开(公告)日：2018-11-28

    申请号：GB201812599

    申请日：2016-11-22

    Applicant: IBM

    Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

    Conformal replacement gate electrode for short channel devices
    3.
    发明专利
    Conformal replacement gate electrode for short channel devices 未知

    公开(公告)号：GB2582080B

    公开(公告)日：2022-03-09

    申请号：GB202007187

    申请日：2018-10-12

    Applicant: IBM ,  ULVAC INC

    Inventor： JOHN ROZEN ,  TAKASHI ANDO ,  VIJAY NARAYANAN ,  RUQIANG BAO ,  YOHEI OGAWA ,  MASANOBU HATANAKA

    IPC: H01L21/8238 ,  H01L29/40

    Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 Å. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.

    Formation of self-aligned bottom spacer for vertical transistors
    4.
    发明专利
    Formation of self-aligned bottom spacer for vertical transistors 未知

    公开(公告)号：GB2581116A

    公开(公告)日：2020-08-05

    申请号：GB202008885

    申请日：2018-12-14

    Applicant: IBM

    Inventor： CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

    IPC: H01L29/78 ,  H01L21/336

    Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

    Semiconductor device having a gate stack with tunable work function
    5.
    发明专利
    Semiconductor device having a gate stack with tunable work function 未知

    公开(公告)号：GB2562948A

    公开(公告)日：2018-11-28

    申请号：GB201812854

    申请日：2017-01-06

    Applicant: IBM

    Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

    Bottom contact resistance reduction on VFET
    6.
    发明专利
    Bottom contact resistance reduction on VFET 未知

    公开(公告)号：GB2575598B

    公开(公告)日：2021-10-06

    申请号：GB201915742

    申请日：2018-04-19

    Applicant: IBM

    Inventor： SHOGO MOCHIZUKI ,  CHOONGHYUN LEE ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

    IPC: H01L29/78

    Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

    Field effect transistor stack with tunable work function
    7.
    发明专利
    Field effect transistor stack with tunable work function 未知

    公开(公告)号：GB2562945B

    公开(公告)日：2020-08-12

    申请号：GB201812599

    申请日：2016-11-22

    Applicant: IBM

    Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

    Vertical transport fin field effect transistors having different channel lengths
    8.
    发明专利
    Vertical transport fin field effect transistors having different channel lengths 未知

    公开(公告)号：GB2578061A

    公开(公告)日：2020-04-15

    申请号：GB202000159

    申请日：2018-06-07

    Applicant: IBM

    Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  CHUN WING YEUNG

    IPC: H01L27/04

    Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

    Semiconductor device having a gate stack with tunable work function
    9.
    发明专利
    Semiconductor device having a gate stack with tunable work function 未知

    公开(公告)号：GB2562948B

    公开(公告)日：2019-06-19

    申请号：GB201812854

    申请日：2017-01-06

    Applicant: IBM

    Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

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