公开(公告)号：JP2007173796A

公开(公告)日：2007-07-05

申请号：JP2006322537

申请日：2006-11-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CALLEGARI ALESSANDRO ,  VIJAY NARAYANAN ,  MICHAEL A GRIBELYUK ,  PARUCHURI VAMSI K ,  ZAFAR SUFI

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: PROBLEM TO BE SOLVED: To provide a new metal compound which is stable to heat on a gate stack containing a high-k dielectric and does not cause carbon diffusion caused in the case of a metal carbide. SOLUTION: This invention provides the metal compound which is a p-type metal having a work function of about 4.75-5.3 eV, preferably about 5 eV and comprises MO x N y stable to heat on the gate stack comprising the high-k dielectric and an interface layer, and a method for manufacturing the MO x N y metal compound. Further, the MO x N y metal compound is an extremely efficient oxygen diffusion barrier at 1,000°C, and achieves, in a p-type metal oxide semiconductor (pMOS) device, an extremely aggressive equivalent oxide film thickness (EOT) and an inversion layer thickness of 14 Å or less. In this formula, M is metal selected from Group IVB, VB, VIB and VIIB of the periodic table of the elements, x is about 5-40 atomic%, and y is about 5-40 atomic%. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供在含有高k电介质的栅极堆叠上对热稳定的新的金属化合物，并且在金属碳化物的情况下不引起碳扩散。 解决方案：本发明提供金属化合物，其为具有约4.75-5.3eV，优选约5eV的功函数的p型金属，并且包括MO x N < / SB>在包含高k电介质和界面层的栅极堆叠上的热稳定，以及用于制造金属化合物的方法。 此外，金属化合物在1000℃下是非常有效的氧扩散阻挡层，并且在p型金属氧化物半导体（pMOS）器件中实现 ，极高的等效氧化膜厚度（EOT）和反射层厚度为14或更小。 在该式中，M是选自元素周期表的IVB，VB，VIB和VIIB族的金属，x为约5-40原子％，y为约5-40原子％。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007184583A

公开(公告)日：2007-07-19

申请号：JP2006343524

申请日：2006-12-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： VIJAY NARAYANAN ,  VAMSI K PARUCHURI ,  CHEN TZE-CHIANG ,  ALESSANDRO CALLEGARI ,  JOSEPH S NEWBURY ,  MICHELLE L STEEN ,  DORIS BRUCE B ,  MICHAEL PATRIK CHUDZIK ,  LINDER BARRY P ,  JOHN C ARNOLD

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: PROBLEM TO BE SOLVED: To provide a CMOS circuit which includes an n-FET gate stack having a gate dielectric and a metal gate conductor, and a p-FET gate stack having a gate dielectric layer and a silicon-containing gate conductor. SOLUTION: In the high-performance complementary metal oxide film semiconductor (CMOS) circuit, each semiconductor unit has at least the first gate stack and the second gate stack. The first gate stack is disposed on a first device region (e.g., n-FET device region) in a semiconductor board, and at least includes a gate dielectric layer 14, a metal gate conductor 16, and a silicon-containing gate conductor 18 that are laminated in increasing order. The second gate stack is disposed on a second device region (e.g., p-FET device region) in the semiconductor board; and at least includes a gate dielectric layer, and a silicon-containing gate conductor that are laminated in increasing order. The first and second gate stacks can be formed on the semiconductor board by a variety of integrated methods. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种CMOS电路，其包括具有栅极电介质和金属栅极导体的n-FET栅极堆叠，以及具有栅极介电层和含硅栅极导体的p-FET栅极堆叠 。 解决方案：在高性能互补金属氧化物半导体（CMOS）电路中，每个半导体单元至少具有第一栅极堆叠和第二栅极堆叠。 第一栅极堆叠设置在半导体板中的第一器件区域（例如，n-FET器件区域）上，并且至少包括栅极电介质层14，金属栅极导体16和含硅栅极导体18， 以增加的顺序层压。 第二栅极堆叠设置在半导体板中的第二器件区域（例如，p-FET器件区域）上; 并且至少包括以增加的顺序层叠的栅极介电层和含硅栅极导体。 第一和第二栅极堆叠可以通过各种集成方法形成在半导体板上。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2010251742A

公开(公告)日：2010-11-04

申请号：JP2010075677

申请日：2010-03-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MO RENEE T ,  CHUDZIK MICHAEL P ,  VIJAY NARAYANAN ,  HENSON WILLIAM K ,  KHARE MUKESH VIJAY ,  BU HUIMING

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a gate structure for improvement in device performance in a metal oxide film semiconductor field-effect transistor.
SOLUTION: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then be formed atop the p-type device regions and n-type device regions of the substrate, and the gate structures to the n-type device regions include a rare-earth metal.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于改善金属氧化物半导体场效应晶体管的器件性能的栅极结构。 解决方案：提供一种形成半导体器件的方法，其包括在基板的p型器件区域的顶部形成Ge含有层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后可以在衬底的p型器件区域和n型器件区域的顶部形成栅极结构，并且到n型器件区域的栅极结构包括稀土金属。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007184584A

公开(公告)日：2007-07-19

申请号：JP2006343832

申请日：2006-12-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN TZE-CHIANG ,  DORIS BRUCE B ,  VAMSI K PARUCHURI ,  MICHAEL PATRIK CHUDZIK ,  VIJAY NARAYANAN ,  MICHELLE L STEEN ,  ALESSANDRO CALLEGARI ,  KIM YOUNG-HEE ,  ZHANG YING

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823857 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To prevent the depletion of the gate polysilicon of a CMOS by a gate electrode structure composed of a metal dielectric stack containing a large volume of potassium. SOLUTION: A semiconductor structure is provided by including an n-FET device and a p-FET device. At least either of the devices includes a gate electrode stack having a thin film of a silicon-containing electrode, i.e., polysilicon electrode and a first metal on the silicon-containing electrode. The other of the devices includes a gate electrode stack not having a thin film of a silicon-containing electrode but at least having a first metal gate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过由含有大量钾的金属电介质堆叠构成的栅电极结构来防止CMOS的栅极多晶硅的耗尽。 解决方案：通过包括n-FET器件和p-FET器件来提供半导体结构。 所述器件中的至少一个包括具有含硅电极的薄膜的栅电极堆叠，即多晶硅电极和含硅电极上的第一金属。 另一个器件包括不具有含硅电极薄膜但至少具有第一金属栅极的栅极电极堆叠。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：GB2577190A

公开(公告)日：2020-03-18

申请号：GB201916582

申请日：2018-05-11

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  TAKASHI ANDO ,  VIJAY NARAYANAN ,  HEMANTH JAGANNATHAN

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal- oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.

公开(公告)号：GB2562945A

公开(公告)日：2018-11-28

申请号：GB201812599

申请日：2016-11-22

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：GB2562945B

公开(公告)日：2020-08-12

申请号：GB201812599

申请日：2016-11-22

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：GB2562948B

公开(公告)日：2019-06-19

申请号：GB201812854

申请日：2017-01-06

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：GB2582080A

公开(公告)日：2020-09-09

申请号：GB202007187

申请日：2018-10-12

Applicant: IBM ,  ULVAC INC

Inventor： JOHN ROZEN ,  TAKASHI ANDO ,  VIJAY NARAYANAN ,  RUQIANG BAO ,  YOHEI OGAWA ,  MASANOBU HATANAKA

IPC: H01L21/8238

Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 2.5 nm. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.

公开(公告)号：GB2560866A

公开(公告)日：2018-09-26

申请号：GB201812607

申请日：2017-01-06

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.