公开(公告)号：CA2103767A1

公开(公告)日：1994-05-10

申请号：CA2103767

申请日：1993-08-10

Applicant: IBM

Inventor： ARIMILLI RAVI K ,  MAULE WARREN E ,  SHIPPY DAVID J ,  SIEGEL DAVID W

IPC: G06F13/12 ,  G06F12/08 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/20

Abstract: CACHE ARCHITECTURE FOR HIGH SPEED MEMORY-TO-I/O DATA TRANSFERS Computer architecture and method of control for accomplishing low speed memory to high speed I/O data transfers. An I/O cache is connected between the memory data bus and a system I/O data bus, and is responsive to a storage control unit which manages data transfers over the system I/O bus. The relatively lower speed of the system memory is offset by the larger size of the memory data bus in comparison to the system I/O data bus. The I/O cache is used to prefetch memory data during read cycles, which prefetch operates in concurrence with the transfer of previously prefetched data from the I/o cache to I/O control units on the system I/O data bus. During the writing of data from I/O to system memory, the I/O cache buffers memory access interferences initiated by the processor. The invention permits the use of a conventional and relatively slow main memory in conjunction with a high speed processor and high speed I/O system.