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    Method and system for supplier-based memory speculation in memory subsystem of data processing system
    3.
    发明专利
    Method and system for supplier-based memory speculation in memory subsystem of data processing system 有权
    用于数据处理系统的存储器子系统中基于供应商的存储器规范的方法和系统

    公开(公告)号：JP2005174342A

    公开(公告)日：2005-06-30

    申请号：JP2004356060

    申请日：2004-12-08

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： ARIMILLI RAVI KUMAR ,  GHAI SANJEEV ,  MAULE WARREN E

    IPC: G06F12/08 ,  G06F9/38 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06

    CPC classification number: G06F9/383 ,  G06F9/3832 ,  G06F9/3851 ,  G06F12/0215

    Abstract: PROBLEM TO BE SOLVED: To provide a method and system for reducing apparent memory access wait time. SOLUTION: A data processing system includes one or more processing cores, a system memory having a plurality of rows of data storage apparatuses, and a memory controller which controls an access to the system memory and performs supplier-based memory speculation. In response to a memory access request, the memory controller directs an access to a selected row, in the system memory to service the memory access request. In order to reduce the access waiting time, immediately after the memory access, the memory controller speculatively directs that the selected row will continue to be energized following the acess, based on the history information in the memory speculation table, even after the access. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种减少表观存储器访问等待时间的方法和系统。 解决方案：数据处理系统包括一个或多个处理核心，具有多行数据存储装置的系统存储器，以及控制对系统存储器的访问并执行基于供应商的存储器推测的存储器控​​制器。 响应于存储器访问请求，存储器控制器指导对系统存储器中的所选行的访问以服务存储器访问请求。 为了减少访问等待时间，在存储器访问之后，存储器控制器推测地指示即使在访问之后，基于存储器猜测表中的历史信息，所选行将在acess之后继续被通电。 版权所有（C）2005，JPO＆NCIPI

    CACHE ARCHITECTURE FOR HIGH SPEED MEMORY-TO-I/O DATA TRANSFERS
    4.
    发明专利
    CACHE ARCHITECTURE FOR HIGH SPEED MEMORY-TO-I/O DATA TRANSFERS 未知

    公开(公告)号：CA2103767A1

    公开(公告)日：1994-05-10

    申请号：CA2103767

    申请日：1993-08-10

    Applicant: IBM

    Inventor： ARIMILLI RAVI K ,  MAULE WARREN E ,  SHIPPY DAVID J ,  SIEGEL DAVID W

    IPC: G06F13/12 ,  G06F12/08 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/20

    Abstract: CACHE ARCHITECTURE FOR HIGH SPEED MEMORY-TO-I/O DATA TRANSFERS Computer architecture and method of control for accomplishing low speed memory to high speed I/O data transfers. An I/O cache is connected between the memory data bus and a system I/O data bus, and is responsive to a storage control unit which manages data transfers over the system I/O bus. The relatively lower speed of the system memory is offset by the larger size of the memory data bus in comparison to the system I/O data bus. The I/O cache is used to prefetch memory data during read cycles, which prefetch operates in concurrence with the transfer of previously prefetched data from the I/o cache to I/O control units on the system I/O data bus. During the writing of data from I/O to system memory, the I/O cache buffers memory access interferences initiated by the processor. The invention permits the use of a conventional and relatively slow main memory in conjunction with a high speed processor and high speed I/O system.

    Absichern der Inhalte einer Speichereinheit
    6.
    发明专利
    Absichern der Inhalte einer Speichereinheit 未知

    公开(公告)号：DE112014000311B4

    公开(公告)日：2021-10-07

    申请号：DE112014000311

    申请日：2014-01-30

    Applicant: IBM

    Inventor： FRANCESCHINI MICHELE M ,  HUNTER HILLERY C ,  JAGMOHAN ASHISH ,  KILMER CHARLES A ,  KIM KYUHYOUN ,  LASTRAS-MONTANO LUIS A ,  MAULE WARREN E

    IPC: G06F12/14 ,  G11B7/26

    Abstract: Dynamische Direktzugriffsspeicher- (DRAM-) Einheit (100; 200), aufweisend:ein Matrixfeld (105; 205) auf der DRAM-Einheit zum Speichern von Daten, wobei das Matrixfeld zwei oder mehr Zeilen (110) enthält, wobei jede Zeile zwei oder mehr Speicherzellen aufweist;einen Zeilenversionsspeicher auf der DRAM-Einheit für jede Zeile des Arrays, um einen Zeilenversionswert (112; 212) zu speichern; einen Gruppenversionsdatenspeicher (101; 201) auf der DRAM-Einheit zum Speichern eines Gruppenversionswerts (102; 202);und einen Sicherheitscontroller (220) in der DRAM-Einheit, der konfiguriert ist, auf den Empfang einer Löschanforderung zu antworten, indem der Lesezugriff für alle Zeilen des Matrixfelds der DRAM-Einheit gesperrt wird und der Gruppenversionswert in einen neuen Gruppenversionswert geändert wird, wobei es nicht zulässig ist, einen Gruppenversionswert festzulegen, der im Gruppenversionsdatenspeicher gespeichert ist.

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