公开(公告)号：WO9611430A3

公开(公告)日：1996-07-18

申请号：PCT/IB9500910

申请日：1995-09-22

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： ARIMILLI RAVI K ,  DODSON JOHN S ,  GUTHRIE GUY ,  LEWIS JERRY D

IPC: G06F12/08 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40 ,  G06F15/16 ,  G06F15/177

CPC classification number: G06F12/0835 ,  G06F13/28 ,  G06F13/405 ,  G06F13/4059

Abstract: An I/O channel controller implements coherency and synchronization mechanisms, which allow the I/O channel controller to provide fully coherent direct memory access operations on a multiprocessor system bus, without implementing a retry protocol. This is made possible by performing delayed cache invalidates for real-time cache coherency conflicts between processors and I/O devices. Furthermore, I/O DMA writes occur real-time to the memory system and without the traditional Read With Intent to Modify (RWITM) operations. Completion of PIO operations has been coupled to the completion of I/O DMA writes operations in order to provide 'seamless' I/O synchronization with respect to processor execution. An IOCC implementation has been described which benefits from those techniques by significantly reducing design complexity.

公开(公告)号：JP2006323845A

公开(公告)日：2006-11-30

申请号：JP2006135600

申请日：2006-05-15

Applicant: IBM

Inventor： ARIMILLI RAVI K ,  WILLIAMS DEREK E

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide a processor, data processing system, and method for initializing a memory block within the data processing system. SOLUTION: In response to receiving an initialization operation from an associated processor core that indicates a target memory block to be initialized, a cache memory determines a coherency state of the target memory block. In response to a determination that the target memory block has a data-invalid coherency state with respect to the cache memory, the cache memory issues on interconnection a corresponding initialization request indicating the target memory block. In response to the initialization request, the target memory block is initialized to an initialization value within a memory of the data processing system. The target memory block may thus be initialized without the cache memory holding a valid copy of the target memory block. COPYRIGHT: (C)2007,JPO&INPIT

公开(公告)号：CA2125218A1

公开(公告)日：1995-03-21

申请号：CA2125218

申请日：1994-06-06

Applicant: IBM

Inventor： ARIMILLI RAVI K ,  GREGOIRE DENNIS G ,  YOUNGS AMY M

IPC: G06F12/08 ,  G06F13/20

Abstract: DYNAMIC MANAGEMENT OF SNOOP GRANULARITY FOR A COHERENT ASYNCHRONOUS DMA CACHE A system and method dynamically changes the snoop comparison granularity between a sector and a page, depending upon the state (active or inactive) of a direct memory access (DMA) I/O device which is writing to a device on the system bus asynchronously when compared to the CPU clock. By using page address granularity, erroneous snoop hits will not occur, since potentially invalid sector addresses are not used during the snoop comparison. Sector memory addresses may be in a transition state at the time when the CPU clock determines a snoop comparison is to occur, because this sector address has been requested by a device operating asynchronously with the CPU clock. Once the asynchronous device becomes inactive the system dynamically returns to a page and sector address snoop comparison granularity.

公开(公告)号：CA2231361A1

公开(公告)日：1998-10-14

申请号：CA2231361

申请日：1998-03-09

Applicant: IBM

Inventor： LEWIS JERRY D ,  DODSON JOHN S ,  ARIMILLI RAVI K

IPC: G06F12/08 ,  G06F9/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/42

Abstract: A method and system for speculatively sourcing cache memory data from a processing unit to an intelligent I/O device within a data-processing system is disclosed. In accordance with the method and system of the present invention, a data-proces sing system includes at least one processing unit, each having at least one cache mem ory and at least one intelligent I/O device. In response to a request for data by an intelligent I/O device within the data-processing system, an intervention respon se is issued from a processing unit within the data-processing system having the reque sted data. The requested data is then read from a cache memory within the processing unit before a combined response from all processing units within the data-processing system returns to the processing unit.

公开(公告)号：CA2103767A1

公开(公告)日：1994-05-10

申请号：CA2103767

申请日：1993-08-10

Applicant: IBM

Inventor： ARIMILLI RAVI K ,  MAULE WARREN E ,  SHIPPY DAVID J ,  SIEGEL DAVID W

IPC: G06F13/12 ,  G06F12/08 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/20

Abstract: CACHE ARCHITECTURE FOR HIGH SPEED MEMORY-TO-I/O DATA TRANSFERS Computer architecture and method of control for accomplishing low speed memory to high speed I/O data transfers. An I/O cache is connected between the memory data bus and a system I/O data bus, and is responsive to a storage control unit which manages data transfers over the system I/O bus. The relatively lower speed of the system memory is offset by the larger size of the memory data bus in comparison to the system I/O data bus. The I/O cache is used to prefetch memory data during read cycles, which prefetch operates in concurrence with the transfer of previously prefetched data from the I/o cache to I/O control units on the system I/O data bus. During the writing of data from I/O to system memory, the I/O cache buffers memory access interferences initiated by the processor. The invention permits the use of a conventional and relatively slow main memory in conjunction with a high speed processor and high speed I/O system.

公开(公告)号：ES2164781T3

公开(公告)日：2002-03-01

申请号：ES95933585

申请日：1995-09-22

Applicant: IBM

Inventor： ARIMILLI RAVI K ,  DODSON JOHN S ,  GUTHRIE GUY ,  LEWIS JERRY D

IPC: G06F12/08 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40 ,  G06F15/16 ,  G06F15/177

Abstract: An I/O channel controller implements coherency and synchronization mechanisms, which allow the I/O channel controller to provide fully coherent direct memory access operations on a multiprocessor system bus, without implementing a retry protocol. This is made possible by performing delayed cache invalidates for real-time cache coherency conflicts between processors and I/O devices. Furthermore, I/O DMA writes occur real-time to the memory system and without the traditional Read With Intent to Modify (RWITM) operations. Completion of PIO operations has been coupled to the completion of I/O DMA writes operations in order to provide "seamless" I/O synchronization with respect to processor execution. An IOCC implementation has been described which benefits from those techniques by significantly reducing design complexity.

公开(公告)号：AT210855T

公开(公告)日：2001-12-15

申请号：AT95933585

申请日：1995-09-22

Applicant: IBM

Inventor： ARIMILLI RAVI K ,  DODSON JOHN S ,  GUTHRIE GUY ,  LEWIS JERRY D

IPC: G06F12/08 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40 ,  G06F15/16 ,  G06F15/177

Abstract: An I/O channel controller implements coherency and synchronization mechanisms, which allow the I/O channel controller to provide fully coherent direct memory access operations on a multiprocessor system bus, without implementing a retry protocol. This is made possible by performing delayed cache invalidates for real-time cache coherency conflicts between processors and I/O devices. Furthermore, I/O DMA writes occur real-time to the memory system and without the traditional Read With Intent to Modify (RWITM) operations. Completion of PIO operations has been coupled to the completion of I/O DMA writes operations in order to provide "seamless" I/O synchronization with respect to processor execution. An IOCC implementation has been described which benefits from those techniques by significantly reducing design complexity.