公开(公告)号：JPH10254677A

公开(公告)日：1998-09-25

申请号：JP3480198

申请日：1998-02-17

Applicant: IBM

Inventor： SOELL WERNER ,  WENDEL DIETER ,  WERNICKE FRIEDRICH-CHRISTIAN

IPC: G06F5/06 ,  G06F5/10 ,  G06F7/74

Abstract: PROBLEM TO BE SOLVED: To inhibit a selected entry which has no priority by determining the priority of an entry in a cyclic buffer wherein an entry should meet given reference with respect to a cyclic buffer which includes a sequence of entries. SOLUTION: An in pointer 103 and an out pointer 104 are provided which allow the cyclic buffer 100 to operate as an FIFO buffer. When the cyclic buffer 110 is full, the in pointer 105 defines the head of a stored entry sequence. In contrast, the tail of the entry sequence is defined by the out pointer 106 which indicates the 1st occupied entry position which is the oldest entry position of the sequence of entry positions. An entry determined by the out pointer 106 is selected each time an entry of the FIFO which should exit from the FIFO is selected. Then the out pointer 106 id increased and a new unoccupied entry position becomes usable.

公开(公告)号：JPH10240524A

公开(公告)日：1998-09-11

申请号：JP2892698

申请日：1998-02-10

Applicant: IBM

Inventor： HILGENDORF ROLF ,  SCHWERMER HARTMUT ,  SOELL WERNER

IPC: G06F9/318

Abstract: PROBLEM TO BE SOLVED: To obtain the possibility of parallel decoding of instructions and to make easy alterations of a conversion path by using reconstitution information corresponding to the instruction of the code and reconstituting instruction elements of the instruction of the code according to the reconstitution information. SOLUTION: The reconstitution information needed to convert an external instruction 100 into one group of internal instructions 101 is included in a conversion table 106. Respective entries 105 of the table 106 correspond to one instruction 100 of an external code to determine how instruction elements of this specific instruction should be reconstituted to form corresponding internal instructions 101. Then the elements of the external instruction like immediate data 110, logical register identifiers 111 and 112, status information, and others 113 and 114 are reconstituted by one group of multiplexers 120 to 124. The outputs of the respective multiplexers are written directly in corresponding fields.