公开(公告)号：EP1869595A4

公开(公告)日：2009-12-16

申请号：EP05855609

申请日：2005-12-22

Applicant: IBM

Inventor： ADKISSON JAMES W ,  BAZAN GREG ,  COHN JOHN M ,  GRADY MATTHEW S ,  SOPCHAK THOMAS G ,  VALLETT DAVID P

IPC: G06F17/50 ,  G03F1/00

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2006107356A3

公开(公告)日：2007-11-22

申请号：PCT/US2005047083

申请日：2005-12-22

Applicant: IBM ,  ADKISSON JAMES W ,  BAZAN GREG ,  COHN JOHN M ,  GRADY MATTHEW S ,  SOPCHAK THOMAS G ,  VALLETT DAVID P

Inventor： ADKISSON JAMES W ,  BAZAN GREG ,  COHN JOHN M ,  GRADY MATTHEW S ,  SOPCHAK THOMAS G ,  VALLETT DAVID P

IPC: G06F17/50 ,  G03F1/00

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design (300) of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shaped (305) between the adjacent integrated circuit elements based on fill shape rules (310), the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes (320) of a monitor structure (315) in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

Abstract translation: 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）产生集成电路的集成电路设计（300）的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模水平设计的区域，所指定的区域足够大，以便基于填充形状规则（310）在相邻集成电路元件之间放置填充形状（305），填充形状不 为集成电路的运行所需; 以及（c）将监视器结构（315）的一个或多个监视器结构形状（320）放置在所述指定区域中的至少一个中，所述监视器结构不是用于所述集成电路的操作所需要的。