公开(公告)号：EP1839338A4

公开(公告)日：2011-11-09

申请号：EP05854112

申请日：2005-12-14

Applicant: IBM

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

IPC: H01L29/04 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

公开(公告)号：EP1869595A4

公开(公告)日：2009-12-16

申请号：EP05855609

申请日：2005-12-22

Applicant: IBM

Inventor： ADKISSON JAMES W ,  BAZAN GREG ,  COHN JOHN M ,  GRADY MATTHEW S ,  SOPCHAK THOMAS G ,  VALLETT DAVID P

IPC: G06F17/50 ,  G03F1/00

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1817801A4

公开(公告)日：2010-07-28

申请号：EP05851917

申请日：2005-11-18

Applicant: IBM

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  STAMPER ANTHONY K

IPC: H01L31/062 ,  H01L21/00

CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

公开(公告)号：JP2007158342A

公开(公告)日：2007-06-21

申请号：JP2006326844

申请日：2006-12-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  HAUSER MICHAEL J ,  ADKISSON JAMES W ,  RANKIN JED H ,  GAUTHIER ROBERT J JR ,  CHATTY KIRAN V ,  JEFFREY SCOTT BROWN ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/14 ,  H01L31/12

CPC classification number: H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of executing an electrical function such as a fusing operation by activation through a chip-embedded photodiode through spectrally selected external light activation, a corresponding structure, and a corresponding circuit. SOLUTION: In conjunction with additional circuit elements to an integrated circuit, incident light with specific intensity/wave length characteristics performs the implementation of repairs. More specifically, failing circuit elements are replaced with redundant ones for yield and/or reliability, and, after a packaged chip is placed in the system, the incident light makes an ESD protection device be disconnected from input pad. No additional pins on the package are necessary. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过光谱选择的外部光激活，对应的结构和相应的电路来通过芯片嵌入式光电二极管的激活来执行诸如定影操作之类的电功能的方法。

解决方案：结合集成电路的附加电路元件，具有特定强度/波长特性的入射光执行维修。 更具体地，用于产生和/或可靠性的冗余电路元件被替换，并且在将封装芯片放置在系统中之后，入射光使得ESD保护装置与输入焊盘断开连接。 不需要额外的引脚。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006339643A

公开(公告)日：2006-12-14

申请号：JP2006148898

申请日：2006-05-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ADKISSON JAMES W ,  JAFFE MARK D ,  LEIDY ROBERT K

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683

Abstract: PROBLEM TO BE SOLVED: To provide an isolation structure used to isolate a pixel sensor device including a selectively doped sidewall.
SOLUTION: A new pixel sensor structure formed on a first conductive-type substrate includes a second conductive-type photosensitive device and a first conductive-type surface pinning layer 180a. The isolation structure 101a is formed adjacent to a photosensitive device pinning layer. The isolation structure includes a dopant region containing a first conductive-type material selectively formed along sidewalls 105a, 105b of the isolation structure where the surface pinning layer is adapted so as to electrically connected to a substrate 150 located beneath. A suitable method for forming the dopant region selectively formed along the sidewall of the isolation structure includes an externally diffusing process that the dopant material present in a material layer formed and doped along a selected portion of the isolation structure is driven into the substrate located beneath during annealing.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于隔离包括选择性掺杂侧壁的像素传感器装置的隔离结构。 解决方案：形成在第一导电型衬底上的新的像素传感器结构包括第二导电型光敏器件和第一导电型表面钉扎层180a。 隔离结构101a形成在与感光装置钉扎层相邻的位置。 隔离结构包括掺杂区域，该掺杂剂区域包含选择性地沿隔离结构的侧壁105a，105b形成的第一导电型材料，其中表面钉扎层适于电连接到位于下面的基底150。 用于形成沿着隔离结构的侧壁选择性形成的掺杂剂区域的合适方法包括外部扩散过程，其中存在于沿着隔离结构的选定部分形成并掺杂的材料层中的掺杂剂材料被驱动到位于下面的衬底中 退火。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2013089938A2

公开(公告)日：2013-06-20

申请号：PCT/US2012063508

申请日：2012-11-05

Applicant: IBM

Inventor： ADKISSON JAMES W ,  DUNBAR THOMAS J ,  GAMBINO JEFFREY P ,  LEITCH MOLLY J

IPC: H01L29/78 ,  B82Y99/00 ,  H01L21/336

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/186 ,  H01L27/1222 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: Manufacturing a semiconductor structure (5) including: forming a seed material (25) on a sidewall of a mandrel (20a, 20b); forming a graphene field effect transistor (FET) (30) on the seed material (25); and removing the seed material (25).

Abstract translation: 制造半导体结构（5），包括：在心轴（20a，20b）的侧壁上形成种子材料（25）; 在种子材料（25）上形成石墨烯场效应晶体管（FET）（30）; 并除去种子材料（25）。

公开(公告)号：JP2002198538A

公开(公告)日：2002-07-12

申请号：JP2001319845

申请日：2001-10-17

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  ARNE W BALLANTINE ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate transistor having a relatively thin epitaxial growth channel. SOLUTION: The epitaxial growth channel is formed, and then a damascene gate is formed, thus forming a silicon-on-insulator(SOI) MOSFET of a dual gate. In the dual-gate MOSFET, a narrow channel should be provided, thus increasing a current drive per layout width, and achieving low out conductance.

公开(公告)号：JP2002134631A

公开(公告)日：2002-05-10

申请号：JP2001300150

申请日：2001-09-28

Applicant: IBM

Inventor： ADKISSON JAMES W ,  RAMACHANDORA DEIVAKARUNI ,  JEFFREY P GANBINO ,  MANDELMAN JACK A

IPC: H01L27/10 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that comprises an embedded DRAM device and a logic device, and to provide a its manufacturing method. SOLUTION: This device comprises a monocrystal substrate having an almost flat surface, a first surface region on the flat surface having a silicon on insulator region, a second surface region on the flat surface which is a monocrystal bulk region, an embeded logic device which is formed in the silicon on insulator region, an embedded memory device which is formed in the monocrystal bulk region, and a trench in the bulk monocrystal region.

公开(公告)号：WO2012047509A3

公开(公告)日：2012-05-31

申请号：PCT/US2011052436

申请日：2011-09-21

Applicant: IBM ,  ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  RASSEL RICHARD J

Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  RASSEL RICHARD J

IPC: H04N5/357 ,  H01L27/146 ,  H04N5/359 ,  H04N5/361 ,  H04N5/376

CPC classification number: H04N5/3595 ,  H01L27/14603 ,  H01L27/14609 ,  H04N5/3532 ,  H04N5/359 ,  H04N5/3745 ,  H04N5/378

Abstract: A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided., A pixel array includes one or more reference pixel sensor ceils (5') dispersed locally throughout active light sensing regions (5). The one or more reference pixel sensor cells provides reference signal (Vdd or REFERENCE) used, to correct for photon generated leakage signals which vary by locality within the active light sensing regions.

Abstract translation: 提供了具有用于泄漏消除的保持节点，制造方法和设计结构的参考像素传感器单元（例如，全局快门），A像素阵列包括在主动光感测区域局部分散的一个或多个参考像素传感器细胞（5'） （5）。 一个或多个参考像素传感器单元提供使用的参考信号（Vdd或REFERENCE），以校正由有源光感测区域内的位置变化的光子产生的泄漏信号。

公开(公告)号：WO2006107356A3

公开(公告)日：2007-11-22

申请号：PCT/US2005047083

申请日：2005-12-22

Applicant: IBM ,  ADKISSON JAMES W ,  BAZAN GREG ,  COHN JOHN M ,  GRADY MATTHEW S ,  SOPCHAK THOMAS G ,  VALLETT DAVID P

Inventor： ADKISSON JAMES W ,  BAZAN GREG ,  COHN JOHN M ,  GRADY MATTHEW S ,  SOPCHAK THOMAS G ,  VALLETT DAVID P

IPC: G06F17/50 ,  G03F1/00

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design (300) of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shaped (305) between the adjacent integrated circuit elements based on fill shape rules (310), the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes (320) of a monitor structure (315) in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

Abstract translation: 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）产生集成电路的集成电路设计（300）的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模水平设计的区域，所指定的区域足够大，以便基于填充形状规则（310）在相邻集成电路元件之间放置填充形状（305），填充形状不 为集成电路的运行所需; 以及（c）将监视器结构（315）的一个或多个监视器结构形状（320）放置在所述指定区域中的至少一个中，所述监视器结构不是用于所述集成电路的操作所需要的。