High resolution lenses for optical waveguides
    1.
    发明授权
    High resolution lenses for optical waveguides 失效
    用于光波导的高分辨率镜头

    公开(公告)号:US3917384A

    公开(公告)日:1975-11-04

    申请号:US39615673

    申请日:1973-09-11

    Applicant: IBM

    CPC classification number: G02B6/1245

    Abstract: A spherical depression lens is formed in a spherical depression in the substrate of the waveguide and a waveguide index lens is formed over the depression lens whereby the combination of the two lenses provides a high resolution waveguide lens for optical waveguides.

    Abstract translation: 球面凹陷透镜形成在波导衬底中的球形凹陷处,并且在凹陷透镜之上形成波导折射透镜,由此两个透镜的组合为光波导提供高分辨率波导透镜。

    Low-loss reflection coatings using absorbing materials
    2.
    发明授权
    Low-loss reflection coatings using absorbing materials 失效
    使用吸收材料的低损耗反射涂层

    公开(公告)号:US3887261A

    公开(公告)日:1975-06-03

    申请号:US34440573

    申请日:1973-03-23

    Applicant: IBM

    CPC classification number: G02B5/0891 G02B5/283 G02B5/288

    Abstract: A class of multi-layer reflectors using a plurality of low-loss reflective elements composed of absorbing materials in the form of thin films is described wherein the differences between the absorption indices of the materials are used to obtain reflecting boundaries. The class of reflector structures are designed in such a manner that when light is directed onto the structure, a standing wave is generated throughout the structure. Absorbing materials in the nodes of the standing wave do not absorb but absorbing materials in the antinodes provide enhanced absorption.

    Abstract translation: 描述了一类使用由薄膜形式的吸收材料构成的多个低损耗反射元件的多层反射器,其中使用材料的吸收指数之间的差异来获得反射边界。 反射器结构的类别被设计成当光被引导到结构上时,在整个结构中产生驻波。 吸收在驻波节点的材料不吸收,但是在波腹中吸收材料提供增强的吸收。

    3.
    发明专利
    未知

    公开(公告)号:FR2316634A1

    公开(公告)日:1977-01-28

    申请号:FR7616137

    申请日:1976-05-21

    Applicant: IBM

    Abstract: A method of constructing masks characterized by a high aspect ratio. The method includes at least a single exposure of a mask by radiation which is transmitted by the substrate before impinging on the resist. In a specific embodiment the mask is partially completed and the already deposited mask modulates the radiation transmitted by the substrate before it exposes the resist.

    5.
    发明专利
    未知

    公开(公告)号:IT8020412D0

    公开(公告)日:1980-03-07

    申请号:IT2041280

    申请日:1980-03-07

    Applicant: IBM

    Abstract: A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors (MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isolation and interconnection of single devices into large circuits on a semiconductor chip.

    6.
    发明专利
    未知

    公开(公告)号:IT1151056B

    公开(公告)日:1986-12-17

    申请号:IT2041280

    申请日:1980-03-07

    Applicant: IBM

    Abstract: A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors (MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isolation and interconnection of single devices into large circuits on a semiconductor chip.

    METHOD FOR FABRICATING SELF-ALIGNED HIGH RESOLUTION NON PLANAR DEVICES EMPLOYING LOW RESOLUTION REGISTRATION

    公开(公告)号:CA1126876A

    公开(公告)日:1982-06-29

    申请号:CA345149

    申请日:1980-02-06

    Applicant: IBM

    Abstract: METHOD FOR FABRICATING SELF-ALIGNED HIGH RESOLUTION NON PLANAR DEVICES EMPLOYING LOW RESOLUTION REGISTRATION A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors(MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device YO978-012 elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isolation and interconnection of single devices into large circuits on a semiconductor chip. YO978-012

    9.
    发明专利
    未知

    公开(公告)号:DE2628467A1

    公开(公告)日:1977-01-27

    申请号:DE2628467

    申请日:1976-06-25

    Applicant: IBM

    Abstract: A positive resist image is produced by exposing, to radiation in a predetermined pattern, a polymeric material containing polymerized alkyl methacrylate units and polymerized monoethylenically unsaturated acid units. The exposed and unexposed areas are distinguished by their different respective abilities to be swelled in an appropriate swelling agent, and the swelled areas are removed by dispersal in a nonsolvent liquid.

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