2.
    发明专利
    未知

    公开(公告)号:DE69123884T2

    公开(公告)日:1997-07-17

    申请号:DE69123884

    申请日:1991-06-11

    Applicant: IBM

    Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material (24) such as silicon dioxide is deposited over the entire substrate (10) on which the devices are formed. A layer of silicon (26) is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions (12, 20) to be connected. The etch-stop material (24) at those regions is then removed. Following this a high-conductivity material (34), which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions (12, 20).

    3.
    发明专利
    未知

    公开(公告)号:DE69123884D1

    公开(公告)日:1997-02-13

    申请号:DE69123884

    申请日:1991-06-11

    Applicant: IBM

    Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material (24) such as silicon dioxide is deposited over the entire substrate (10) on which the devices are formed. A layer of silicon (26) is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions (12, 20) to be connected. The etch-stop material (24) at those regions is then removed. Following this a high-conductivity material (34), which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions (12, 20).

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