公开(公告)号：EP0814497A2

公开(公告)日：1997-12-29

申请号：EP97304224

申请日：1997-06-17

Applicant: SIEMENS AG ,  TOSHIBA KK ,  IBM

Inventor： ALSMEIER JOHANN ,  COTE DONNA R ,  LOH STEPHEN K ,  PARRIES PAUL C ,  GIFFORD GEORGE G ,  PREIN FRANK ,  LEVY MAX G ,  SUGIURA SOICHI

IPC: C23C16/30 ,  C23C16/56 ,  H01L21/205 ,  H01L21/28 ,  H01L21/30 ,  H01L21/31 ,  H01L21/318 ,  H01L21/336 ,  H01L23/31 ,  H01L29/78 ,  H01L21/22

CPC classification number: H01L29/66575 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/3185 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A process for fabricating a device including the step of forming a structure for facilitating the passivation of surface states is disclosed. The structure comprises a hydrogen-rich (H-R) silicon nitride layer formed as part of the device structure. The H-R layer, which is formed by plasma-enhanced chemical vapor deposition, comprises hydrogen in an amount greater than that of conventional PLCVD nitride layers.

Abstract translation: 公开了一种用于制造包括形成用于促进表面状态钝化的结构的步骤的装置的方法。 该结构包括作为器件结构的一部分形成的富氢（H-R）氮化硅层。 通过等离子体增强化学气相沉积形成的H-R层包含比常规PLCVD氮化物层大的量的氢。

公开(公告)号：WO2012012154A3

公开(公告)日：2012-04-26

申请号：PCT/US2011042289

申请日：2011-06-29

Applicant: IBM ,  KWON OH-JUNG ,  LEE JUNEDONG ,  PARRIES PAUL C ,  SCHEPIS DOMINIC J

Inventor： KWON OH-JUNG ,  LEE JUNEDONG ,  PARRIES PAUL C ,  SCHEPIS DOMINIC J

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Abstract translation: 提供了用于制造隔离电容器的结构和方法。 该方法包括通过SOI和掺杂多晶层同时形成围绕多个深沟槽的组或阵列的多个深沟槽和一个或多个隔离沟槽至下伏绝缘体层。 该方法还包括用绝缘体材料衬里多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成将一个或多个深沟槽电容器的组或阵列与深沟槽电容器的另一组或阵列隔离的一个或多个隔离板。

公开(公告)号：CA2061119C

公开(公告)日：1998-02-03

申请号：CA2061119

申请日：1992-02-12

Applicant: IBM

Inventor： PENNINGTON SCOTT L ,  RYAN JAMES G ,  LICATA THOMAS J ,  LEE PEI-ING P ,  PARRIES PAUL C ,  MCDEVITT THOMAS L ,  STRIPPE DAVID C

IPC: C23C14/46 ,  C23C14/04 ,  H01L21/203 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H05K3/40 ,  C23C14/34

Abstract: A sputtering deposition wherein high aspect ratio apertures are coated with conductive films exhibiting low bulk resistivity, low impurity concentrations, and regular morphologies. A collimator is used having an aspect ratio that approximates the aspect ratio of the apertures. The resulting film thickness at the bottom of the aperture is at least 2X what can be achieved using conventional sputtering methods.

公开(公告)号：GB2495457A

公开(公告)日：2013-04-10

申请号：GB201301679

申请日：2011-06-29

Applicant: IBM

Inventor： KWON OH-JUNG ,  LEE JUNEDONG ,  PARRIES PAUL C ,  SCHEPIS DOMINIC J

IPC: H01L27/108 ,  H01L21/762

Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

公开(公告)号：DE3883185T2

公开(公告)日：1994-03-17

申请号：DE3883185

申请日：1988-11-30

Applicant: IBM

Inventor： CRITCHLOW DALE L ,  DEBROSSE JOHN K ,  MOHLER RICK L ,  NOBLE WENDELL P ,  PARRIES PAUL C

IPC: H01L21/28 ,  H01L21/74 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

公开(公告)号：DE3883185D1

公开(公告)日：1993-09-16

申请号：DE3883185

申请日：1988-11-30

Applicant: IBM

Inventor： CRITCHLOW DALE L ,  DEBROSSE JOHN K ,  MOHLER RICK L ,  NOBLE WENDELL P ,  PARRIES PAUL C

IPC: H01L21/28 ,  H01L21/74 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

公开(公告)号：CA2043172A1

公开(公告)日：1991-12-29

申请号：CA2043172

申请日：1991-05-24

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  MANN RANDY W ,  PARRIES PAUL C ,  SPRINGER JULIE A

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.

公开(公告)号：GB2495457B

公开(公告)日：2014-08-20

申请号：GB201301679

申请日：2011-06-29

Applicant: IBM

Inventor： KWON OH-JUNG ,  LEE JUNEDONG ,  PARRIES PAUL C ,  SCHEPIS DOMINIC J

IPC: H01L27/108 ,  H01L21/762

公开(公告)号：DE112011102414T5

公开(公告)日：2013-06-06

申请号：DE112011102414

申请日：2011-06-29

Applicant: IBM

Inventor： KWON OH-JUNG ,  LEE JUNEDONG ,  PARRIES PAUL C ,  SCHEPIS DOMINIC J

IPC: H01L21/84 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

Abstract: Es wird eine Struktur und ein Verfahren zur Herstellung isolierter Kondensatoren bereitgestellt. Das Verfahren weist das gleichzeitige Bilden mehrerer tiefer Gräben und eines oder mehrerer Isolationsgräben, welche eine Gruppe oder ein Feld der mehreren tiefen Gräben umgeben, durch eine SOI- und dotierte Polyschicht zu einer darunter liegenden Isolatorschicht auf. Das Verfahren weist ferner das Auskleiden der mehreren tiefen Gräben und des einen oder der mehreren Isolationsgräben mit einem Isolatormaterial auf. Das Verfahren weist ferner das Füllen der mehreren tiefen Gräben und des einen oder der mehreren Isolationsgräben mit einem leitfähigen Material auf dem Isolatormaterial auf. Die tiefen Gräben bilden Tiefgrabenkondensatoren, und der eine oder die mehreren Isolationsgräben bilden eine oder mehrere Isolationsplatten, welche mindestens eine Gruppe oder ein Feld der Tiefgrabenkondensatoren von einer anderen Gruppe oder einem Feld der Tiefgrabenkondensatoren isolieren.

公开(公告)号：CA2061119A1

公开(公告)日：1992-10-20

申请号：CA2061119

申请日：1992-02-12

Applicant: IBM

Inventor： LEE PEI-ING P ,  LICATA THOMAS J ,  MCDEVITT THOMAS L ,  PARRIES PAUL C ,  PENNINGTON SCOTT L ,  RYAN JAMES G ,  STRIPPE DAVID C

IPC: C23C14/46 ,  C23C14/04 ,  H01L21/203 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H05K3/40 ,  C23C14/34

Abstract: A sputtering deposition wherein high aspect ratio apertures (50) are coated with conductive films (40) exhibiting low bulk resistivity, low impurity concentrations, and regular morphologies. A collimator (60) is used having an aspect ratio that approximates the aspect ratio of the apertures (50). The resulting film thickness at the bottom of the aperture is at least 2X what can be achieved using conventional sputtering methods.