公开(公告)号：JPS61296709A

公开(公告)日：1986-12-27

申请号：JP14039686

申请日：1986-06-18

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  LASKY JEROME B ,  NESBIT LARRY A ,  SEDGWICK THOMAS O ,  STIFFLER SCOTT R

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12

公开(公告)号：CA1218762A

公开(公告)日：1987-03-03

申请号：CA495661

申请日：1985-11-19

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  LASKY JEROME B ,  NESBIT LARRY A ,  SEDGWICK THOMAS O ,  STIFFLER SCOTT R

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/306

Abstract: A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer. The silicon substrate is removed using grinding and/or HNA, the upper portions of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop is removed using a non-selective etch. The remaining portions of the epitaxy forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness. BU9-84-031

公开(公告)号：DE69123884T2

公开(公告)日：1997-07-17

申请号：DE69123884

申请日：1991-06-11

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  MANN RANDY W ,  PARRIES PAUL C ,  SPRINGER JULIE A

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/60 ,  H01L23/485

Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material (24) such as silicon dioxide is deposited over the entire substrate (10) on which the devices are formed. A layer of silicon (26) is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions (12, 20) to be connected. The etch-stop material (24) at those regions is then removed. Following this a high-conductivity material (34), which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions (12, 20).

公开(公告)号：DE69123884D1

公开(公告)日：1997-02-13

申请号：DE69123884

申请日：1991-06-11

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  MANN RANDY W ,  PARRIES PAUL C ,  SPRINGER JULIE A

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/60 ,  H01L23/485

Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material (24) such as silicon dioxide is deposited over the entire substrate (10) on which the devices are formed. A layer of silicon (26) is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions (12, 20) to be connected. The etch-stop material (24) at those regions is then removed. Following this a high-conductivity material (34), which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions (12, 20).

公开(公告)号：CA2043172C

公开(公告)日：1996-04-09

申请号：CA2043172

申请日：1991-05-24

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  MANN RANDY W ,  PARRIES PAUL C ,  SPRINGER JULIE A

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L23/522

Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.

公开(公告)号：DE69220393T2

公开(公告)日：1998-01-15

申请号：DE69220393

申请日：1992-02-04

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  DAUBENSPECK TIMOTHY H ,  LUCE STEPHEN E ,  POLEY DENIS J ,  PREVITI-KELLEY ROSEMARY A ,  VIENS GARY P ,  YOON JUNG H

IPC: G03F7/11 ,  G03F7/09 ,  G03F7/36 ,  H01L21/027

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

公开(公告)号：DE69220393D1

公开(公告)日：1997-07-24

申请号：DE69220393

申请日：1992-02-04

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  DAUBENSPECK TIMOTHY H ,  LUCE STEPHEN E ,  POLEY DENIS J ,  PREVITI-KELLEY ROSEMARY A ,  VIENS GARY P ,  YOON JUNG H

IPC: G03F7/11 ,  G03F7/09 ,  G03F7/36 ,  H01L21/027

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

公开(公告)号：CA2043172A1

公开(公告)日：1991-12-29

申请号：CA2043172

申请日：1991-05-24

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  MANN RANDY W ,  PARRIES PAUL C ,  SPRINGER JULIE A

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.

公开(公告)号：CA1208805A

公开(公告)日：1986-07-29

申请号：CA481991

申请日：1985-05-21

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  KOBURGER CHARLES W III

IPC: H01L27/08 ,  H01L21/20 ,  H01L21/225 ,  H01L21/76 ,  H01L21/762 ,  H01L29/78

Abstract: VERTICALLY ISOLATED COMPLEMENTARY TRANSISTORS A process for making complementary transistor devices in an epitaxial layer of a first conductivity type having a deep vertical isolation sidewall between the N and P channel transistors by providing a backfilled cavity in the epitaxial layer, the sidewalls of the cavity being coated with layers of material, the first layer being a silicate doped with the same conductivity type as the epitaxial layer in contact with the epitaxial layer and overcoated with an isolation and diffusion barrier layer, the second silicate layer doped to a conductivity opposite to that of the first layer and isolated therefrom by said isolation and diffusion barrier material. The cavity is backfilled with semiconductor material of a conductivity type opposite to that of the epitaxial layer and during this backfilling operation the dopants in the first and second layer outdiffuse into the epitaxial layer and into the backfill material respectfully to prevent the creations of parasitic channels.