公开(公告)号：GB1168414A

公开(公告)日：1969-10-22

申请号：GB3545768

申请日：1968-07-25

Applicant: IBM

Inventor： ARULPRAGASAM JEGANANDARAJ AMAL ,  BINKS DENNIS CRAVEN ,  PINNELL MARTIN COXWELL ,  PRICE RICHARD LOWELL ,  TUFFILL HAROLD WILLIAM ,  VASILE VINCENT CHARLES ,  WAUGH ROBIN

IPC: G06F11/14 ,  G06F11/20

Abstract: 1,168,414. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 25 July, 1968, No. 35457/68. Heading G4A. In a data processing system, recovery log storage is connected via a recovery log buffer to predetermined data locations in a C.P.U. (central processing unit) for recording data therefrom, and is updated after predetermined intervals but only after error checking circuitry in the C.P.U. has indicated error-free data flow in the C.P.U. during the current interval. The output of main storage goes via error-correcting circuitry to both the C.P.U. and a main storage buffer (which holds the 7 latest items from main storage and their addresses). Instruction fetch and execution cycles occur alternately. Changes in various C.P.U. registers during execution cycles are followed by a recovery log buffer the contents of which are passed to the recovery log storage during the respective following fetch cycles except that detection of an error in the C.P.U. during an execution cycle freezes the recovery log buffer, recovery log storage and main storage buffer to permit subsequent resumption of the programme or instruction retry without data loss. The recovery log buffer may be an associative store holding only the new contents of the portions of the C.P.U. registers which have actually changed, together with tags identifying the register portions. The recovery log arrangements, including the main storage buffer, have a separate power supply. Changes in the C.P.U. during fetch cycles may be stored in the recovery log storage during execution cycles.

公开(公告)号：GB1163859A

公开(公告)日：1969-09-10

申请号：GB3442968

申请日：1968-07-19

Applicant: IBM

Inventor： ARULPRAGASAM JEGANANDARAJ AMAL ,  MINSHULL JOHN FRANCIS ,  PINNELL MARTIN COXWELL ,  GLOVER ALAN CHARLES ,  TUFFILL HAROLD WILLIAM ,  WAUGH ROBIN

IPC: G06F11/14 ,  G06F11/20

Abstract: 1,163,859. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 19 July, 1968, No. 34429/68. Heading G4A. In a data processing system, a recovery log unit maintains a profile of a first CPU (central processing unit) updated to a time before error is detected in the first CPU, and detection of error in the first CPU causes a second CPU to process the profile into storable form and store it in common main storage. The profile is all information necessary to permit a cleared CPU to continue its programme where it left off, including information of pending interrupts. Detection of error prevents further updating of the profile, and an error which persists despite instruction retry, or power failure, causes the second CPU to process the profile as stated above. The second CPU has its own recovery log unit and is normally concerned with its own tasks, and when required to process the profile of the other CPU as above, it temporarily stores its own working section in the main storage. The second CPU may take over the tasks of the first, using the profile of the first, in which case it processes its own profile and stores it in the main storage. The first CPU can perform for the second the services which the second is described above as performing for the first, and further CPU's can be provided. A profile can be forced into the system for diagnostic purposes.

公开(公告)号：GB1153420A

公开(公告)日：1969-05-29

申请号：GB2217768

申请日：1968-05-10

Applicant: IBM

Inventor： ARULPRAGASAM JEGANANDARAJ AMAL ,  HOCKINGS MICHAEL LE HEGARAT KI ,  MINSHULL JOHN FRANCIS ,  PINNELL MARTIN COXWELL ,  STAFFORD THOMAS SANDERSON

IPC: G06F9/48

Abstract: 1,153,420. Computer interrupt. INTERNATIONAL BUSINESS MACHINES CORP. 10 May, 1968, No. 22177/68. Heading G4A. In a data processing system, an interrupt condition causes the status of the current programme to be stored in a first area, a second area to be allocated to a new programme, and the address of the first area to be entered into the second area. In a two-processor microprogramme-controlled system, the highest priority interrupt request not masked by a status register selects a double-word from a (stored) interrupt list according to the class of interrupt. The doubleword includes a bit-pair and an address. If the bit-pair is 01, 10 or 11, the address is that of an interrupt class list. If the bit-pair is 01, the interrupt code (which gives details of the interrupt) is shifted and used to select another double-word from the interrupt class list. If the bit-pair is 10, the interrupt code is decremented by a so-called "mask" in the interrupt class list and one of two double-words selected from this list according as the result is negative or not. If the bit-pair is 11, the interrupt code is ANDed with the "mask" and one of the two doublewords selected according as the result is zero or not. If the bit-pair is 00, the address is that of a status load block. In this way a sequence of one or more double-words is selected until one is reached with the bit-pair 00 to obtain the address of a status load block. In the above, if the interrupt code is decremented, it is the decremented interrupt code which is used, if necessary, in connection with the next double-word, but if it is ANDed, it is the code before ANDing which is used. The status load block is used to initialize the system to execute the programme for dealing with the interrupt, after storing the current status data (relating to the interrupted programme) in a current programme status block (storage area), to enable subsequent resumption of the interrupted programme. A programme status block is obtained for the new programme, the address of this block being obtained from the head of the interrupt list which specifies the address of the first block of a free list of such blocks, each block in the list containing the address of the next so that they are chained together. The "first block" address in the interrupt list is then updated. While the interrupt list is being used by one processor, a lock byte and the identity of the processor are stored in it (the list) to prevent the other processor using it and to enable this processor to find out why use is prevented. The programme status block (which is loaded With status data for its programme when that programme is interrupted) holds interrupt masking bits, storage protection key (for comparison with a key associated with each block of storage to prevent access unless they are equal or one is zero), instruction length indicator, indication of conditions which will cause branch, next instruction address, indications of which local storage registers have had their contents saved (determined by the doubleword with bit-pair 00 referred to above), addresses of locations where various registers can be dumped in the event of an interrupt, the address of the programme status block of the previously running programme, class of interrupt, identity of processor to which the current interruption is related, interrupt code, and extended interrupt code giving more information on the interrupt. Provision is made for dealing with exhaustion of the free list. Conventional types of interrupt are described. The interrupt list, interrupt class lists and status load blocks are settable under control of a supervisor programme. Besides the two processors, the system includes two memories with a unified addressing scheme and the effective configuration of the system is controlled by configuration control data stored in the various units.