Single-phase charge-coupled semiconductor device
    1.
    发明授权
    Single-phase charge-coupled semiconductor device 失效
    单相电荷耦合半导体器件

    公开(公告)号:US3796933A

    公开(公告)日:1974-03-12

    申请号:US3796933D

    申请日:1971-11-10

    Applicant: IBM

    CPC classification number: H01L29/42396 H01L29/435 H01L29/76866

    Abstract: A charge-coupled semiconductor device for transmitting information in the form of mobile charges through a depletion layer which comprises an electrode structure on the surface of a semiconductor body that has within it an elongated region containing an impurity gradient. When the body is biased to create a depletion under the region and packets of charges are introduced into the body near the region, the charges will under the influence of the field gradients in the depletion layer be caused to pass through the body, in a known period of time. If due to space charge broadening the charge packets slowly spread out, they may be regrouped by applying a single clock pulse to the electrode structure, which will create sharply defined potential wells under the impurity gradient. The device is particularly useful as both a delay line and as a simple, fast, reliable, memory array.

    SINGLE-PHASE CHARGE-COUPLED SEMICONDUCTOR DEVICE

    公开(公告)号:CA966229A

    公开(公告)日:1975-04-15

    申请号:CA156033

    申请日:1972-11-08

    Applicant: IBM

    Abstract: 1383977 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 18 Oct 1972 [10 Nov 1971] 47952/72 Heading H1K In a semi-conductor device, such as a shift register or delay line, utilizing the drift of an injected group 30 of minority-charge carriers through a depletion region 23À1 induced in a substrate 10À1 beneath an electrode structure 20À1, there is provided a graded-impurityconcentration region 17À1 of the same conductivity type as the substrate 10À1. The region 17À1 is graded in such a way that in the presence of the appropriate operating voltages on the substrate electrode 21À1, electrode structure 20À1, injecting electrode 15À1 and detecting electrode 16À1. The boundary of the depletion region 23À1 extends parallel to the device surface. In the Si shift register illustrated the electrode structure 20À1 comprises a plurality of interconnected A1 strips capacitively coupled to the ion implanted region 17À1 through a SiO2 layer 18À1. For P-type material a negative bias on the substrate electrode 21À1 induces the depletion region 23À1, the presence of the grounded strips 20À1 producing shallow potential wells 25 which are rapidly filled with injected charge-carriers. A subsequently injected charge-carrier group 30 will drift along the depletion region 23À1, but will tend to become progressively loss spatially localized due to space charge spreading. The group 30 is periodically reshaped by the application of a positive clock pulse to the electrode structure 20À1. Such a pulse temporarily deepens the potential walls 25, causing the drifting group 30 to be trapped and hence relocalized. Using this techique charge-carrier groups may be directed around carriers and in opposed directions. In a simplified embodiment constituting a delay line the electrode structure 20À1 is replaced by a single continuous electrode (20), Fig. 1 (not shown), overlying the whole length of the graded region (17À1), there being in this case no localized potential walls to reshape an injected pulse.

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