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公开(公告)号：WO02057924A3
公开(公告)日：2003-06-26
申请号：PCT/GB0200123
申请日：2002-01-15
Inventor： CRANFORD HAYDEN CLAVIE , NORMAN VERNON ROBERTS , SCHMATZ MARTIN LEO
CPC classification number: H03L7/08 , H03L7/095 , H03L7/0995 , H03L7/10 , H04L7/0337 , H04L2027/0067
Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL) , a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
Abstract translation: 描述了统一的单向串行链路，用于通过诸如芯片到芯片或卡到卡互连的有线介质提供数据。 它由一个传输部分和一个接收部分组成，它们被成对地运行以允许串行数据通信。 串行链路作为VLSI ASIC模块的一部分实现，并从主机模块中获得其功率，数据和时钟要求。 逻辑发送器部分包含锁相环（PLL），双位数据寄存器，有限脉冲响应（FIR）滤波器和发送数据寄存器。 锁相环包括数字粗回路和模拟精密回路。 数字接收机部分包含PLL，FIR相位旋转器，相位旋转器控制状态机和时钟缓冲器。 发射机和接收机各自优选地利用伪随机比特流（PRBS）生成器和检查器。
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公开(公告)号：WO02058355A3
公开(公告)日：2003-02-20
申请号：PCT/GB0200128
申请日：2002-01-15
Inventor： CRANFORD HAYDEN CLAVIE , NORMAN VERNON ROBERTS , SCHMATZ MARTIN LEO
CPC classification number: G06F13/423
Abstract: A global architecture for a serial link connection between two cards which must transmit data across wired media is provided. The architecture comprises a transmitter portion and a receiver portion. The transmitter portion includes a structure and circuitry to take digital bits from a first bit register, such as for example, an eight-bit register or a ten-bit register, and convert these bits into serial analog transmission to the receiver portion. The receiver portion includes a structure and circuitry to sample the analog transmission of the original digital bits and reconvert the analog serial signal of the digital bits corresponding to the original digital bits and store them in a second bit register comparable to the data stored in the original register from which they were selected.
Abstract translation: 提供了必须通过有线媒体传输数据的两张卡之间的串行链路连接的全球架构。 该架构包括发射机部分和接收机部分。 发送器部分包括从第一位寄存器（例如，八位寄存器或十位寄存器）获取数字位的结构和电路，并将这些位转换成到接收器部分的串行模拟传输。 接收器部分包括对原始数字位的模拟传输进行采样并重新对应于原始数字位的数字位的模拟串行信号的结构和电路，并将其存储在与存储在原始数据中的数据相当的第二位寄存器中 他们被选中的注册表。
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Patent Agency Ranking
公开(公告)号：DE60227048D1
公开(公告)日：2008-07-24
申请号：DE60227048
申请日：2002-01-15
Applicant: IBM
Inventor： CRANFORD HAYDEN CLAVIE , NORMAN VERNON ROBERTS , SCHMATZ MARTIN LEO
Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
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公开(公告)号：DE3176416D1
公开(公告)日：1987-10-08
申请号：DE3176416
申请日：1981-05-19
Applicant: IBM
IPC: G11C17/00 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L27/10 , H01L29/60
Abstract: In the electrically alterable read only memory cell a reduction in cell area and an improvement in tolerance allowed for programming and erase voltages is achieved utilizing a diffused control gate (3) having improved capacitive coupling to the floating gate (7) through a thin oxide layer (5) grown on single crystal silicon (1). A thin oxide layer (6) is also grown over the channel area (2). Polyoxide layers (8) and (10) isolate the programming gate (9) from the floating gate (7) and the latter from the erase gate (11). The ratio of thickness between the oxide layers (5) and (6) and the polyoxide layers (8) and (10) is of one to four or five.
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公开(公告)号：DE3272406D1
公开(公告)日：1986-09-11
申请号：DE3272406
申请日：1982-02-10
Applicant: IBM
IPC: H01L21/8236 , H01L27/088 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/78 , H03K17/10 , H03K17/687 , H03K19/0944 , H03K17/12 , H03K19/094
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公开(公告)号：AT330362T
公开(公告)日：2006-07-15
申请号：AT02716131
申请日：2002-01-15
Applicant: IBM
Inventor： CRANFORD HAYDEN CLAVIE , GARVIN STACY JEAN , NORMAN VERNON ROBERTS , OWCZARSKI PAUL ALAN , SCHMATZ MARTIN LEO , STEVENS JOSEPH MARSH
Abstract: The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
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公开(公告)号：AU2002219371A1
公开(公告)日：2002-07-30
申请号：AU2002219371
申请日：2002-01-15
Applicant: IBM
Inventor： NORMAN VERNON ROBERTS , CRANFORD HAYDEN CLAVIE , SCHMATZ MARTIN LEO
Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
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