公开(公告)号：WO2007042428A2

公开(公告)日：2007-04-19

申请号：PCT/EP2006066999

申请日：2006-10-03

Applicant: IBM ,  IBM UK ,  BARTLEY GERALD KEITH ,  BORKENHAGEN JOHN MICHAEL ,  HOVIS WILLIAM PAUL ,  KOLZ DANIEL PAUL

Inventor： BARTLEY GERALD KEITH ,  BORKENHAGEN JOHN MICHAEL ,  HOVIS WILLIAM PAUL ,  KOLZ DANIEL PAUL

CPC classification number: G06F13/28

Abstract: An apparatus includes a virtual memory manager that moves data from a first block (A) to a second block (B) in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block (C) of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.

Abstract translation: 一种装置包括将数据从第一块（A）移动到存储器中的第二块（B）的虚拟存储器管理器。 当虚拟存储器管理器准备好将数据从第一块传送到第二块时，定义了第三个临时块（C）。 将DMA控制器中的转换表更改为将目标为第一个块的DMA传输指向临时块。 然后，虚拟存储器管理器将数据从第一块传送到第二块。 当传输完成时，检查DMA是否将数据传输到临时块，而第一个块的数据正在写入第二个块。 如果是这样，则将写入临时块的数据写入第二块。 优选地使用硬件寄存器来有效地检测对临时块的改变。

公开(公告)号：JP2008021314A

公开(公告)日：2008-01-31

申请号：JP2007182029

申请日：2007-07-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GERMANN PHILIP RAYMOND ,  BORKENHAGEN JOHN M ,  GERALD KEITH BARTLEY ,  HOVIS WILLIAM PAUL

IPC: G06F12/06 ,  G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F13/161 ,  G06F12/08 ,  G06F12/122

Abstract: PROBLEM TO BE SOLVED: To provide a multilevel memory architecture with data prioritization. SOLUTION: In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有数据优先级的多级存储器架构。 解决方案：在控制包括多个存储器位置的计算机可读存储器的方法中，确定存储在第一存储器位置中的数据单元的使用频率。 数据单元被移动到不同于基于第二存储器位置的已知等待时间与数据单元的使用频率之间的对应关系而选择的第一存储器位置的第二存储器位置，其中第二存储器位置是主要的 数据单元的数据存储位置。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006252696A

公开(公告)日：2006-09-21

申请号：JP2005069170

申请日：2005-03-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AIPPERSPACH ANTHONY GUS ,  HOVIS WILLIAM PAUL ,  KUEPER TERRANCE WAYNE ,  SHEETS JOHN EDWARD II

IPC: G11C11/413

Abstract: PROBLEM TO BE SOLVED: To provide a method and an apparatus enabling an electronic system implemented using a field effect transistor (FET) to reduce a threshold voltage shift due to bias temperature instability (BTI).
SOLUTION: The VT shift due to BTI is accumulated when a FET is in a particular voltage stress state. A number of memory elements in the electronic system store the same data over substantially the life of the system. As a result, the VT shift due to BTI significantly occurs in a FET in the memory element. An embodiment of the present invention guarantees that a specific memory element is in a first state for a first portion of the time for which the electronic system is operated, and data is stored in a first phase in the memory element for the period of time, and a specific memory element is in a second state for a second portion of the time for which the electronic system is operated, and data is stored in a second phase in the memory element for the period of time.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供使得能够使用场效应晶体管（FET）实现的电子系统能够减少由于偏置温度不稳定性（BTI）导致的阈值电压偏移的方法和装置。 解决方案：当FET处于特定的电压应力状态时，由于BTI引起的VT移位被累积。 电子系统中的许多存储元件在系统的基本寿命内存储相同的数据。 结果，由于BTI引起的VT偏移显着地发生在存储元件中的FET中。 本发明的实施例保证了特定的存储元件在电子系统操作的时间的第一部分处于第一状态，并且数据在存储元件中的第一阶段被存储一段时间， 并且对于电子系统操作的时间的第二部分，特定存储器元件处于第二状态，并且数据被存储在存储元件中的第二阶段一段时间。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2008234662A

公开(公告)日：2008-10-02

申请号：JP2008074311

申请日：2008-03-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GERMANN PHILIP RAYMOND ,  BORKENHAGEN JOHN M ,  BECKER DARRYL J ,  BARTLEY GERALD KEITH ,  HOVIS WILLIAM PAUL

IPC: G06F12/06 ,  G06F1/32 ,  G11C11/401 ,  G11C11/407

CPC classification number: Y02D10/13

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for implementing power saving in addressing of a DRAM device. SOLUTION: A random access memory device includes an array of individual memory cells arranged into rows and columns, and each memory cell has a corresponding access device. Assuming N as the number corresponding to the number of independently accessible partitions of the array, each row of the array further includes a corresponding plurality of N word lines, and each access device in a given row is coupled to only one of the N word lines of the rows. An address decoder communicating with the array receives a plurality of row address bits, and determines which of the N partitions in a requested row must be accessed on the requested row identified by the row address bits, and does not activate the access device within the selected row but not within the partition to be accessed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在DRAM设备的寻址中实现省电的结构和方法。 解决方案：随机存取存储器件包括排列成行和列的各个存储单元的阵列，并且每个存储单元具有对应的存取设备。 假设N为与阵列的独立可访问分区的数量相对应的数字，阵列的每一行还包括相应的多个N个字线，并且给定行中的每个访问设备仅耦合到N个字线中的一个 的行。 与阵列通信的地址解码器接收多个行地址位，并且确定在所请求的行中必须在由行地址位标识的所请求的行上访问所述N个分区中的哪一个，并且不激活所选行中的访问设备 行，但不在要访问的分区内。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2002324399A

公开(公告)日：2002-11-08

申请号：JP2002052065

申请日：2002-02-27

Applicant: IBM

Inventor： HOVIS WILLIAM PAUL ,  STEVEN WILLIAM TOMASHOT

IPC: G11C11/407 ,  G06F12/00 ,  G11C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a clocked memory device that contains programming mechanisms to set a write recovery time as a function of input clocks. SOLUTION: The clocked memory device contains programming mechanisms that permit setting the write recovery time dynamically as some function of input clocks. In one of the preferred implementations, the programming mechanisms contain a control register, which has programmable bits that can specify the write recovery time responding to their bit value. For instance, it can specify the write recovery time as a multiple of integer or fraction of clock cycles. Specifying a write recovery time as a function of clock that can be specified dynamically makes it possible to use the clocked memory device at its highest performing capability over a wide range of operating frequency.

公开(公告)号：DE69123372D1

公开(公告)日：1997-01-16

申请号：DE69123372

申请日：1991-01-24

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：DE69022975D1

公开(公告)日：1995-11-16

申请号：DE69022975

申请日：1990-11-17

Applicant: IBM

Inventor： BUSCH ROBERT EDWARD ,  HOVIS WILLIAM PAUL ,  REDMAN THEODORE MILTON ,  THOMA ENDRE PHILIP ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/00 ,  G11C11/409 ,  G11C11/407

Abstract: A method and device for setting at lease three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.

公开(公告)号：DE602006010893D1

公开(公告)日：2010-01-14

申请号：DE602006010893

申请日：2006-10-03

Applicant: IBM

Inventor： BARTLEY GERALD KEITH ,  BORKENHAGEN JOHN MICHAEL ,  HOVIS WILLIAM PAUL ,  KOLZ DANIEL PAUL

IPC: G06F13/28

公开(公告)号：DE69119258T2

公开(公告)日：1996-11-21

申请号：DE69119258

申请日：1991-01-19

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  YANKOSKY JAMES ANDREW

IPC: G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

Abstract: Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).

公开(公告)号：DE69119258D1

公开(公告)日：1996-06-13

申请号：DE69119258

申请日：1991-01-19

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  YANKOSKY JAMES ANDREW

IPC: G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

Abstract: Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).