公开(公告)号：GB2579487A

公开(公告)日：2020-06-24

申请号：GB202001682

申请日：2018-07-16

Applicant: IBM ,  GLOBALFOUNDRIES INC ,  SAMSUNG ELECTRONICS CO LTD

Inventor： SU CHEN FAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ANDREW GREENE ,  RUILONG XIE ,  MARK VICTOR RAYMOND ,  SEAN LIAN

IPC: H01L21/8238

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided, in one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers In a dielectric; forming gate trenches by selectively rernoving the dielectric from: regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：GB2577197B

公开(公告)日：2020-08-05

申请号：GB201916897

申请日：2018-04-19

Applicant: IBM

Inventor： ZUOGUANG LIU ,  SU CHEN FAN ,  HENG WU ,  TENKO YAMASHITA

IPC: H01L29/66 ,  H01L21/74 ,  H01L21/768 ,  H01L29/41 ,  H01L29/78

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.

公开(公告)号：GB2579487B

公开(公告)日：2021-12-15

申请号：GB202001682

申请日：2018-07-16

Applicant: IBM ,  GLOBALFOUNDRIES INC ,  SAMSUNG ELECTRONICS CO LTD

Inventor： SU CHEN FAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ANDREW GREENE ,  RUILONG XIE ,  MARK VICTOR RAYMOND ,  SEAN LIAN

IPC: H01L21/768 ,  H01L21/8238

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：GB2577197A

公开(公告)日：2020-03-18

申请号：GB201916897

申请日：2018-04-19

Applicant: IBM

Inventor： ZUOGUANG LIU ,  SU CHEN FAN ,  HENG WU ,  TENKO YAMASHITA

IPC: H01L29/66 ,  H01L21/74 ,  H01L21/768 ,  H01L29/41 ,  H01L29/78

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.