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    VFET fin structure
    1.
    发明专利
    VFET fin structure 未知

    公开(公告)号：GB2581893B

    公开(公告)日：2022-04-13

    申请号：GB202006464

    申请日：2018-11-01

    Applicant: IBM

    Inventor： CHEN ZHANG ,  KANGGUO CHENG ,  TENKO YAMASHITA ,  XIN MIAO ,  WENYU XU

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/308 ,  H01L29/06

    Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.

    Dual transport orientation for stacked vertical transport field-effect transistors
    3.
    发明专利
    Dual transport orientation for stacked vertical transport field-effect transistors 未知

    公开(公告)号：GB2595098B

    公开(公告)日：2022-10-26

    申请号：GB202110765

    申请日：2019-12-02

    Applicant: IBM

    Inventor： TENKO YAMASHITA ,  CHEN ZHANG ,  KANGGUO CHENG ,  HENG WU

    IPC: H01L21/02

    Abstract: A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET.

    Stacked vertical transistor memory cell
    4.
    发明专利
    Stacked vertical transistor memory cell 未知

    公开(公告)号：GB2604510A

    公开(公告)日：2022-09-07

    申请号：GB202207100

    申请日：2020-10-16

    Applicant: IBM

    Inventor： CHEN ZHANG ,  TENKO YAMASHITA ,  KANGGUO CHENG ,  HENG WU

    IPC: H01L27/11 ,  G11C11/417 ,  H01L27/11517 ,  H01L27/11551

    Abstract: A semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a bottom tier including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal being electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes a top tier including a at least one top transistor, and a cross-coupling including epitaxial region (epi) connections and gate to epi connections between the top tier and the bottom tier.

    Dual transport orientation for stacked vertical transport field-effect transistors
    5.
    发明专利
    Dual transport orientation for stacked vertical transport field-effect transistors 未知

    公开(公告)号：GB2595098A

    公开(公告)日：2021-11-17

    申请号：GB202110765

    申请日：2019-12-02

    Applicant: IBM

    Inventor： TENKO YAMASHITA ,  CHEN ZHANG ,  KANGGUO CHENG ,  HENG WU

    IPC: H01L21/02

    Abstract: A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET.

    Approach to high-k dielectric feature uniformity
    6.
    发明专利
    Approach to high-k dielectric feature uniformity 未知

    公开(公告)号：GB2581104B

    公开(公告)日：2020-11-18

    申请号：GB202007030

    申请日：2018-10-23

    Applicant: IBM

    Inventor： CHEN ZHANG ,  TENKO YAMASHITA ,  CHUN WING YEUNG

    IPC: H01L29/78

    Abstract: A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a multilayer fin on the doped layer, where the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the upper and lower trim layer portions. A portion of the lower trim layer portion is removed to form a lower trim layer post, and a portion of the upper trim layer portion is removed to form an upper trim layer post. An upper recess filler is formed adjacent to the upper trim layer post, and a lower recess filler is formed adjacent to the lower trim layer post. A portion of the fin channel portion is removed to form a fin channel post between the upper trim layer post and lower trim layer post.

    H-shaped VFET with increased current drivability
    7.
    发明专利
    H-shaped VFET with increased current drivability 未知

    公开(公告)号：GB2581893A

    公开(公告)日：2020-09-02

    申请号：GB202006464

    申请日：2018-11-01

    Applicant: IBM

    Inventor： CHEN ZHANG ,  KANGGUO CHENG ,  TENKO YAMASHITA ,  XIN MIAO ,  WENYU XU

    IPC: H01L29/78

    Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.

    Approach to high-k dielectric feature uniformity
    8.
    发明专利
    Approach to high-k dielectric feature uniformity 未知

    公开(公告)号：GB2581104A

    公开(公告)日：2020-08-05

    申请号：GB202007030

    申请日：2018-10-23

    Applicant: IBM

    Inventor： CHEN ZHANG ,  TENKO YAMASHITA ,  CHUN WING YEUNG

    IPC: H01L29/78

    Abstract: A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a multilayer fin on the doped layer, where the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the upper and lower trim layer portions. A portion of the lower trim layer portion is removed to form a lower trim layer post, and a portion of the upper trim layer portion is removed to form an upper trim layer post. An upper recess filler is formed adjacent to the upper trim layer post, and a lower recess filler is formed adjacent to the lower trim layer post. A portion of the fin channel portion is removed to form a fin channel post between the upper trim layer post and lower trim layer post.

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