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    Stacked nanosheet transistor with defect free channel
    4.
    发明专利
    Stacked nanosheet transistor with defect free channel 未知

    公开(公告)号：GB2628728A

    公开(公告)日：2024-10-02

    申请号：GB202408798

    申请日：2022-11-28

    Applicant: IBM

    Inventor： LAN YU ,  KANGGUO CHENG ,  HENG WU ,  CHEN ZHANG

    IPC: H01L29/66

    Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.

    Phase change memory using multiple stacks of PCM materials
    5.
    发明专利
    Phase change memory using multiple stacks of PCM materials 未知

    公开(公告)号：GB2608308A

    公开(公告)日：2022-12-28

    申请号：GB202213056

    申请日：2021-01-26

    Applicant: IBM

    Inventor： TIAN SHEN ,  HENG WU ,  KEVIN WAYNE BREW ,  JINGYUN ZHANG

    IPC: H01L45/00 ,  G06N3/063 ,  G11C11/56 ,  G11C13/00

    Abstract: A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode (12) over a substrate (10), constructing a PCM stack (20) including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode (12), and forming a top electrode (32) over the PCM stack (20). The crystallization temperature varies in an ascending order from the bottom electrode (12) to the top electrode (32).

    Dual transport orientation for stacked vertical transport field-effect transistors
    8.
    发明专利
    Dual transport orientation for stacked vertical transport field-effect transistors 未知

    公开(公告)号：GB2595098B

    公开(公告)日：2022-10-26

    申请号：GB202110765

    申请日：2019-12-02

    Applicant: IBM

    Inventor： TENKO YAMASHITA ,  CHEN ZHANG ,  KANGGUO CHENG ,  HENG WU

    IPC: H01L21/02

    Abstract: A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET.

    Stacked vertical transistor memory cell
    9.
    发明专利
    Stacked vertical transistor memory cell 未知

    公开(公告)号：GB2604510A

    公开(公告)日：2022-09-07

    申请号：GB202207100

    申请日：2020-10-16

    Applicant: IBM

    Inventor： CHEN ZHANG ,  TENKO YAMASHITA ,  KANGGUO CHENG ,  HENG WU

    IPC: H01L27/11 ,  G11C11/417 ,  H01L27/11517 ,  H01L27/11551

    Abstract: A semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a bottom tier including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal being electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes a top tier including a at least one top transistor, and a cross-coupling including epitaxial region (epi) connections and gate to epi connections between the top tier and the bottom tier.

    Dual transport orientation for stacked vertical transport field-effect transistors
    10.
    发明专利
    Dual transport orientation for stacked vertical transport field-effect transistors 未知

    公开(公告)号：GB2595098A

    公开(公告)日：2021-11-17

    申请号：GB202110765

    申请日：2019-12-02

    Applicant: IBM

    Inventor： TENKO YAMASHITA ,  CHEN ZHANG ,  KANGGUO CHENG ,  HENG WU

    IPC: H01L21/02

    Abstract: A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET.

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