公开(公告)号：JP2004167671A

公开(公告)日：2004-06-17

申请号：JP2003348877

申请日：2003-10-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOCIS JOSEPH T ,  TORNELLO JAMES ,  PETRARCA KEVIN ,  VOLANT RICHARD ,  SUBANNA SESHADRI

IPC: B81C1/00 ,  B81B3/00 ,  H01H50/00

CPC classification number: B81C1/00666 ,  B81B2201/014 ,  B81C2201/0167 ,  H01F2007/068 ,  H01H50/005

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an encapsulated micro electro-mechanical system (MEMS) which causes little metallic fatigue and stress.
SOLUTION: The MEMS manufacturing method includes steps for forming a dielectric layer 204, patterning the upper surface of the first dielectric layer 204 to form a trench, forming a release material 212 in the trench, patterning the upper surface of the release material 212 to form the other trench, forming a first encapsulating layer 222 that includes sidewalls in the other trench, forming a core layer 242 in the first encapsulating layer 222, and forming a second encapsulating layer 262 above the core layer 242 where the second encapsulating layer 262 is connected to sidewalls of the first encapsulating layer 222.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2001267432A

公开(公告)日：2001-09-28

申请号：JP2001051096

申请日：2001-02-26

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  FREEMANN GREGORY GOWER ,  SUBANNA SESHADRI

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a polysilicon-polysilicon capacitor for use in a CMOS or BiCMOS integrated circuit simply and inexpensively. SOLUTION: The method for forming a polysilicon-polysilicon capacitor 49, an MOS transistor 18, and a bipolar transistor 48 simultaneously on a substrate 10 comprises a step for forming a first polysilicon layer on the substrate 10 and patterning it in order to form the first plate electrode of the capacitor 49 and the electrode of the MOS transistor 18, and a step for forming a second polysilicon layer on the substrate 10 and patterning it in order to form the second plate electrode of the capacitor 49 and the electrode of the bipolar transistor 48.

公开(公告)号：DE10107012A1

公开(公告)日：2001-09-13

申请号：DE10107012

申请日：2001-02-15

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  FREEMANN GREGORY GOWER ,  SUBANNA SESHADRI

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/737 ,  H01L27/08

Abstract: The simultaneous formation of a poly-poly capacitor, a MOS transistor and a bipolar transistor on a substrate (10) comprises applying and structuring a first layer made from polycrystalline silicon on the substrate to form a first plate electrode of the capacitor and an electrode of the MOS transistor; and applying and structuring a second layer made from a polycrystalline silicon on the substrate to form a second plate electrode of the capacitor and an electrode of the bipolar transistor. The second polycrystalline layer is made from SiGe-polycrystalline silicon. An Independent claim is also included for the production of a poly-poly capacitor. Preferred Features: The electrode of the MOS transistor comprises a polycrystalline gate (20) formed on a gate oxide (22). The gate oxide is formed on the surface of the substrate and the substrate has source and drain regions (14) below the polycrystalline gate.