公开(公告)号：JPH04229488A

公开(公告)日：1992-08-18

申请号：JP16940591

申请日：1991-06-14

Applicant: IBM

Inventor： BAABARA AREN CHIYATSUPERU ,  TERII AIBUAN CHIYATSUPERU ,  MAHAMUTO KEMARU EBUSHIOGURU ,  SUTANREI EBUERETSUTO SHIYUSUTA

IPC: G06F12/08 ,  G06F12/00 ,  G06F12/04 ,  G06F12/0855 ,  G11C8/12 ,  G11C8/16 ,  G11C11/41

Abstract: PURPOSE: To provide a multiport RAM structure combining speed, density and multi-port function which can not be balanced with both a conventional multiport RAM and a the multidata copy in a conventional single port RAM. CONSTITUTION: The virtual multiport RAM structure 10 executed as a pipelined semiconductor memory chip has multiaddresses respectively multiplexed in address busses and data busses, a single port RAM array being on the chip given by a data input port and an internal timing device on the chip controlling the timing of the single port array and also cycling the multiinput ports in order to perform the multiport RAM function.

公开(公告)号：JPS63157463A

公开(公告)日：1988-06-30

申请号：JP25987787

申请日：1987-10-16

Applicant: IBM

Inventor： UEI WANGU ,  SUTANREI EBUERETSUTO SHIYUSUTA ,  RIYUISU MAJISON TAAMEN

IPC: G11C11/401 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108