公开(公告)号：DE3166926D1

公开(公告)日：1984-12-06

申请号：DE3166926

申请日：1981-05-25

Applicant: IBM

Inventor： CACCOMA GEORGE ANTHONY ,  KOESTNER JOSEPH HENRY ,  O'NEILL BRIAN COLLINS ,  TAPPEN FRANK MUIR

IPC: H01L21/60 ,  H01L21/67 ,  H05K13/04 ,  H01L21/68

Abstract: A batch chip placement system for batch positioning semiconductor chips, or the like, upon a substrate containing an array of chip sites or footprints whose actual position on the substrate deviates from the theoretical or nominal position over successive substrates. The positioning is achieved by first sensing the X and Y offsets of a pair of alignment marks on the substrate from their theoretical or nominal position to determine the DELTA X and DELTA Y correction factors required to obtain the actual X,Y position of the alignment marks. The actual X,Y position of the alignment marks is used to determine actual X,Y chip position values, theta rotation and shrinkage factor corrections required to obtain proper orientation and positioning for batch chip placement.