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5 records (took 0.017 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE2608213A1

    公开(公告)日：1976-10-14

    申请号：DE2608213

    申请日：1976-02-28

    Applicant: IBM

    Inventor： GRIFFITHS DONALD ERIC ,  KOESTNER JOSEPH HENRY ,  NORTON DAVID GIBBONS

    IPC: G11B23/03 ,  G11B17/02 ,  G11B17/038 ,  G11B17/32 ,  G11B17/34 ,  G11B23/00 ,  G11B5/016 ,  G11B17/22

    Abstract: Semi-rigid washers are coaxially disposed to form an air-permeable spindle for coaxially supporting flexible record disks. A plurality of such washers and disks is coaxially stacked to construct a flexible disk file. Washers preferably have an annular shoulder with a depth slightly different than the thickness of the record disks for firmly supporting and aligning same in the coaxial stack. Alternatively, disks may be adhesively secured to a radial outward portion of each washer. Additionally, each washer has a plurality of radially extending air passageways for facilitating radial air movement which controls the stack of flexible record disks. A radial inward portion of each washer abuts each adjacent washer for forming a firm axial stack of disks. A rigid stabilizing plate at each axial end completes the assembly.

    BATCH PLACEMENT SYSTEM FOR ELECTRONIC COMPONENTS OR CHIPS
    4.
    发明专利
    BATCH PLACEMENT SYSTEM FOR ELECTRONIC COMPONENTS OR CHIPS 未知

    公开(公告)号：DE3166926D1

    公开(公告)日：1984-12-06

    申请号：DE3166926

    申请日：1981-05-25

    Applicant: IBM

    Inventor： CACCOMA GEORGE ANTHONY ,  KOESTNER JOSEPH HENRY ,  O'NEILL BRIAN COLLINS ,  TAPPEN FRANK MUIR

    IPC: H01L21/60 ,  H01L21/67 ,  H05K13/04 ,  H01L21/68

    Abstract: A batch chip placement system for batch positioning semiconductor chips, or the like, upon a substrate containing an array of chip sites or footprints whose actual position on the substrate deviates from the theoretical or nominal position over successive substrates. The positioning is achieved by first sensing the X and Y offsets of a pair of alignment marks on the substrate from their theoretical or nominal position to determine the DELTA X and DELTA Y correction factors required to obtain the actual X,Y position of the alignment marks. The actual X,Y position of the alignment marks is used to determine actual X,Y chip position values, theta rotation and shrinkage factor corrections required to obtain proper orientation and positioning for batch chip placement.

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