公开(公告)号：SG111048A1

公开(公告)日：2005-05-30

申请号：SG200201205

申请日：2002-02-28

Applicant: IBM

Inventor： MUKESH KHARE ,  PAUL D AGNELLO ,  ANTHONY I CHOU ,  TERENCE BLACKWELL HOOK ,  ANDA C MOCUTA

IPC: H01L21/74 ,  H01L29/423 ,  H01L29/786 ,  H01L21/786

Abstract: An SOI circuit configuration effective for minimizing plasma-induced charging damage during fabrication comprises the formation of charge collectors connected to the gate electrode and the semiconductor body, wherein each one of the charge collectors have the same or substantially the same shape and dimension. A connecting structure formed between a device fabricated on SOI substrate and substrate is delayed until the latter stages of processing.