公开(公告)号：SG115598A1

公开(公告)日：2005-10-28

申请号：SG200307829

申请日：2003-12-26

Applicant: IBM

Inventor： HEEMYONG PARK ,  BYOUNG H LEE ,  PAUL D AGNELLO ,  DOMINIC J SCHEPIS ,  GHAVAM G SHAHIDI

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L21/28 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/74 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

公开(公告)号：SG111048A1

公开(公告)日：2005-05-30

申请号：SG200201205

申请日：2002-02-28

Applicant: IBM

Inventor： MUKESH KHARE ,  PAUL D AGNELLO ,  ANTHONY I CHOU ,  TERENCE BLACKWELL HOOK ,  ANDA C MOCUTA

IPC: H01L21/74 ,  H01L29/423 ,  H01L29/786 ,  H01L21/786

Abstract: An SOI circuit configuration effective for minimizing plasma-induced charging damage during fabrication comprises the formation of charge collectors connected to the gate electrode and the semiconductor body, wherein each one of the charge collectors have the same or substantially the same shape and dimension. A connecting structure formed between a device fabricated on SOI substrate and substrate is delayed until the latter stages of processing.

公开(公告)号：SG97204A1

公开(公告)日：2003-07-18

申请号：SG200106328

申请日：2001-10-12

Applicant: IBM

Inventor： JAMES W ADKISSON ,  PAUL D AGNELLO ,  ARNE W BALLANTINE ,  RAMA DIVAKARUNI ,  ERIN JONES ,  EDWARD JOSEPH NOWAK ,  JED H RANKIN

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：SG82045A1

公开(公告)日：2001-07-24

申请号：SG1999006335

申请日：1999-12-10

Applicant: IBM

Inventor： PAUL D AGNELLO ,  LEENA P BUCHWALTER ,  JOHN PATRICK HUMMEL ,  BARBARA J LUTHER ,  ANTHONY K STAMPER

IPC: H01L21/04 ,  H01L21/28 ,  H01L23/522 ,  H01L21/318 ,  H01L21/768 ,  H01L21/316 ,  H01L21/325

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure.