公开(公告)号：GB1186704A

公开(公告)日：1970-04-02

申请号：GB998968

申请日：1968-03-01

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY ,  TITMAN PETER JAMES

IPC: G01R19/00 ,  G11C15/04

Abstract: 1,186,704. Transistor switching circuits. INTERNATIONAL BUSINESS MACHINES CORP. 1 March, 1968, No. 9989/68. Heading H3T. [Also in Division G4] In a selection circuit for selecting from an ordered set of electronic components, the next operable component to a component issuing a selection signal, a series-connected chain of impedances is provided with selection signal sense circuits of successive components of the set connected to successive nodes of the chain and a selection signal generator of each component connected to the same node as the sense circuit of the next component of the set, the sense circuit of each inoperable component presenting to a selection signal an impedance substantially greater than that of any impedance of the chain. Word storage locations W0, W1, W2 ... (Fig. 1) of an associative store have respective selector triggers (not shown) to control which locations participate in read and write operations. A " NEXT " operation causes any selector trigger, which is set, to energize the corresponding line 2 and set the selector trigger of the next non-defective word storage location via a generating circuit G, resistor chain R1, R2 ..., a sense circuit S, an AND gate 4 and a transfer trigger (not shown). Fig. 2 shows a generating circuit G(N) comprising long-tailed NPN transistor pair T1, T2, and a sense circuit S(N+ 1) comprising transistor T3, regulating transistor T4 and clamp circuit T5, T6. The sense circuit of a defective word storage location has had its disconnection switches D opened (or fuses blown) previously so the sense circuit presents a high impedance to the resistor chain R1, R2 ... and so is skipped. Each resistor R1, R2 ... may be replaced by two equal resistors in series, with their common terminal clamped. In this case the inverters I of Fig. 1 may be dispensed with so each word storage location can accept a signal through S and AND gate 4 and deliver one through G simultaneously. Each resistor in the chain can be replaced by a diode or a plurality of diodes in parallel. The invention can also be used for skipping defective packages in a series of packages of integrated circuitry used in turn for processing data.

公开(公告)号：GB1218407A

公开(公告)日：1971-01-06

申请号：GB1759770

申请日：1968-07-04

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY ,  TITMAN PETER JAMES ,  LLEWELYN ROGER JAMES

IPC: G06F9/26 ,  G06F15/80 ,  G11C15/04

Abstract: 1,218,407. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 4 July, 1968, No. 17597/70. Divided out of 1,218,406. Heading G4A. In an electronic data processing system, logic and arithmetic functions are performed by table-look-up operations on stored function tables, there being a function store containing function tables, a work store arranged in operation to store operands, and a microprogramme store arranged in operation to emit micro-instructions each including an operation code, the function and work stores comprising respective decoders arranged to decode a part of the operation code particular to the store. The disclosure is essentially included in the parent.

公开(公告)号：GB1127270A

公开(公告)日：1968-09-18

申请号：GB4062367

申请日：1967-09-05

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY ,  TITMAN PETER JAMES

IPC: G11C15/04 ,  H03K3/29

Abstract: 1,127,270. Electric digital data storage. INTERNATIONAL BUSINESS MACHINES CORP. 5 Sept., 1967, No. 40623/67. Heading G4C. [Also in Division H3] A transistor binary storage cell, suitable for an associative store, provides the same first output signal whether it is in its " 1 " state and is interrogated for a "1" or is in its " 0 " state and is interrogated for a " 0 " and has a third state which also provides the first output signal whether it is interrogated for a " 0 " or " 1 ". The cell may have a fourth state which provides a different output signal when so interrogated. The storage cell in Fig. 4 comprises two bi-stable circuits arranged such that in state " 1 " T1 and T2 conduct, state " 0 " T1 and T3 conduct, state " 3 " T2 and T3 conduct and state " 4 " T1 and T4 conduct. Non - destructive interrogation for a " 0 " (i.e. a " 0 " match) is effected by switching the " 0 bit " a line 44 to - 0-2 V at switch 46 and the " 1 bit " line 45 to 0À1 V at switch 47. If the cell is in the " 0 " state transistor T1 is conducting but its emitter current is directed by the operation of switch 46 to emitter E12. T4 is non-conductive so that no current flows to the output line 43 from either transistor, indicating a " 0 " match. If however the circuit is in the " 1 " state the current from T4 is directed to the output line 43 indicating " no match ". Interrogating for a " 1 " match may be similarly effected and produces no current in line 43 if the match conditions exist. If the cell is in the third state neither transistor T1 nor T4 is conducting and no current flows to line 43, indicating "match" whether interrogation is for a " 0 " or a " 1 ". If however it is in the fourth state T1 and T4 both conduct and one or other current is directed to the output line 43 whether interrogation is for a " 0 " or " 1 ", indicating no match. Non-destructive read out may alternatively be effected by closing switch 49 on 0À1 V and switches 46 and 47 on 0 V. Current flowing from T1 or T4 into one or other of the bit lines 44 and 45 indicates the state of the circuit. Writing is effected by applying the interrogating voltage, such as from switches 46 and or/47, to the bit lines and lowering the threshold of the bi-stable circuits by closing switch 48 on the 2.0 V terminal and switch 49 on the 0À1 V terminal so that the transistors are into the conducting or non conducting states corresponding to the positions of switches 46 and 47. The previous state of the cell may first be destroyed by momentarily closing switch 48 on the floating terminal. If switch 49 is moved to the - 0À2 V terminal the data cell is isolated since the bit lines are then ineffective to direct the emitter currents to the output line 43. In Fig. 6 emitter followers are used in the cross couplings (as described with reference to Fig. 5, not shown) to avoid the necessity of hard saturation. In addition switch 48 is replaced by a switch 61 and the collectors of the emitter followers are taken to a tap on the collector resistors of the main transistors T1, T2, T3, T4. Interrogating and writing is carried out in a similar manner to Fig. 4 except that the lowering of the threshold to permit writing is effected by operating switch 61 to - V so as to increase the current through the emitter resistors and reduce the current through resistors R3b and R6b. Fig. 6 shows a circuit having only the first, second and third stable states, the states being represented by one of the main transistors T7, T8 or T9 conducting. These three transistors derive their input through respective emitter followers from the joint output of the other two main transistors so that any one of the main transistors will conduct only when the other two are non-conducting. Interrogating for a " 0 " is effected by placing such voltages on the bit lines 71 and 72 that if current is flowing in transistor T7 it is steered through emitter E71 to the " 0 " bit line to indicate match whereas if current is flowing in transistor T8 it is directed through emitter E82 to the word emitter line 73 to indicate no match. Interrogating for a " 1 " is similarly effected. If the circuit is in the third state (T9 conductive) no significant current reaches the output emitter lines 73 whichever interrogation is carried out and a match signal is indicated. A null interrogation is effected by placing such voltages on the bit lines that no significant current reaches the word emitter line even if T7 or T8 is conducting. Reading is effected by placing such a voltage on the word emitter line 73 that if current is flowing in transistors T7 or T8 it is diverted to the associated bit line to indicate the state of the cell. If T9 is conducting no current will appear on either line. Writing is effected by placing such a voltage on the word emitter line 73 that the switching threshold of transistors T7 and T8 is lowered and placing voltages on the bit lines 44, 45 such as to force the transistors T7 and T8 into the required conducting conditions. The cell is described in relation to an associative store (Fig. 1, not shown) in which the input register (11) is coupled to the columns of the store through a masking register (13). The cell enables one particular data position to be ignored without masking the whole of the column.

公开(公告)号：GB1218406A

公开(公告)日：1971-01-06

申请号：GB3207568

申请日：1968-07-04

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY ,  TITMAN PETER JAMES ,  LLEWELYN ROGER JAMES

IPC: G06F9/26 ,  G06F9/28 ,  G11C15/04

Abstract: 1,218,406. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 4 July, 1968, No. 32075/68. Heading G4A. An electronic data processing system includes two associative stores, data from one being used for an associative search in the other. General.-The system of Fig. 2 has three associative stores 21, 22, 23 each stored word having the fields shown. The local store 23 contains macro-instructions and operands, the working store 22 contains tables and the control store 21 contains sequences of micro-instructions for executing respective macro-instructions. In each store, matching may be done on the complete words or on portions indicated by the " mask " lines, and data read from or written into whole words or the portions not indicated by the respective mask lines. A match can set selectively a primary or a secondary trigger associated with the matched word, or a primary or secondary trigger associated with the next word. Reading and writing occurs with respect to that word or words having selectively either the primary trigger set or ther secondary trigger set, and if there is more than one such word the same data will be written into all such words (on writing) or the data read from the various words (on reading) will be ORed together. The set state of a primary or secondary trigger may be moved to the next such trigger for the same store, by a " next " operation. Each storage cell has three possible states 0, 1, X, the last being a " don't care " state which will match on either 0 or 1 indifferently. The macro-instructions are stored in consecutive locations in the local store, the first having a predetermined L.S. TAG field, successive macro-instructions being obtained by use of the " next " operation to step the set state of a primary trigger to the next primary trigger. The DATA 1 field of the macroinstruction is matched against the C.S. TAG fields of the control store to obtain the first micro-instruction, further micro-instructions being obtained by use of the " next " operation on the primary triggers of the store, similar to above. The L.S. TAG field of a micro-instruction can be matched against the L.S. TAG fields of the local store to obtain operands which are matched against the DATA 0 fields of the working store as the W.S. TAG of the microinstruction is matched against the W.S. TAG fields of the working store. The W.S. TAG applied specifies a stored table and the operands specify a word (or the first of a plurality of consecutive words) therein which contain the result of an operation on the operands (table look-up). The result can be transferred to the local store. The W.S. and L.S. TAGS matched against the working and local stores also control operation of the respective stores, and the control store is controlled by the C.S. OP field from itself. Micro-instruction subroutines can be sequenced through using the secondary triggers of the control store without disturbing the primary triggers used for sequencing through the main microprogramme in which the subroutine is embedded. Specifications 1,127,270 and 1,186,703 are referred to for the associative stores. Further details of table look-up.-Fig. 3 shows part of the working store for performing the AND, OR and EXCL-OR of two 4-bit operands A, B. The operands and a tag (which is 01, 11, 10 for AND, OR, EXCL-OR respectively) are matched against the corresponding " argument " fields shown in each word (row) the " output " fields of matching rows (there will be only one for AND, two for EXCL-OR and three for OR) being read out and ORed together. Shift and addition by table look-up are mentioned. Branch.-Micro-instruction branch is performed by obtaining the next micro-instruction by matching a 4-bit COND field from the working store and the C.S. TAG from the current micro-instruction (modified by ORing with the DATA 1 field from the working store, which will, however, usually be all zeros, or by the DATA 1 field from the local store) against the COND and C.S. TAG fields of the control store. The COND field from the working store indicates machine conditions, e.g. which of two operands is the larger, or overflow during addition. Macro-instruction branch is done similarly (in the local store) except that no COND field is involved. Modifications.-A conventional core store can be provided for holding the macro-instructions, its data input/output and address register both communicating with buses 27, 28 of Fig. 2. The core store is controlled by the W.S. TAGs from the control store (bus 24). An error (e.g. in an address) causes the core store to emit a C.S. TAG on bus 28 to cause entry into a diagnostic routine (no details). The local store holds instruction counts (for obtaining the next macro-instruction from the core store) which can be indexed by +1, +2, or -1 obtained from the working store, the indexing being by table look-up in the working store. The control store may be partly non-associative. Combination with second system.-The above system may be used as an interface between a transmission line and a larger data processing system, data from the line being buffered in the working store, then checked and edited before transfer to the larger system.

公开(公告)号：GB1186703A

公开(公告)日：1970-04-02

申请号：GB4543267

申请日：1967-10-05

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY ,  TITMAN PETER JAMES

IPC: G11C15/04

Abstract: 1,186,703. Associative stores; computers. INTERNATIONAL BUSINESS MACHINES CORP. 5 Oct., 1967, No. 45432/67. Headings G4A and G4C. In an associative memory, each word store has a plurality of bi-stable devices associated with it, setting of ;any one of which enables a read or write signal subsequently to be applied to the word store, selection means being provided to set a selectable one of the bi-stable devices in response to the generation of a match signal. The associative store of Fig. 1 comprises: an input register 2; a mask register (with gates) 4; logic circuits 6; word stores 7 each bit position being capable of three states viz. 0, 1, nothing; a primary and a secondary trigger 16, 17 respectively (with logic) associated with each word store; an output register 9; and a decoder 19 which can produce any of the following operations: SELECT: those orders of the input register 2 which correspond to orders of the mask register 4 set at 1 are compared with corresponding orders of the word stores 7 (decoder output S energized), match setting either the primary or the secondary trigger (according as decoder output P or SY is energized). SELECT NEXT: like " select " only the primary or secondary trigger of the next word store is set on match, not that of the word store giving the match (decoder output N also energized). TRANSFER TO NEXT: the set state of each set primary or secondary trigger (depending on whether P or SY is energized) is transferred to the next such trigger (N energized). READ: those word stores whose primary or secondary triggers (depending on P or SY) are set are read out to the output register 9 simultaneously (so that if there are a plurality of such word stores corresponding bits are ORed on the column lines 11, 12) and in any event only those positions at which the mask register 4 holds 0 are gated at 71 to the output register 9 (decoder output R energized). WRITE: contents of input register 2 at those orders corresponding to orders of the mask register 4 set at 0 are written into those word stores having the primary or secondary trigger set (depending on P or SY; W also energized). SET MASK: input register 2 loads the mask register 4 (SM energized). SWITCH: output SW of decoder 19 is energized to overrule the selective effects of the mask register 4. Combinations of the above operations are possible. In a computer, accessing of instruction words belonging to the main programme and to subroutines may be controlled by the primary and secondary triggers respectively TRANSFER TO NEXT followed by READ can be used for stepping through a set of consecutive instructions, a branch being initiated by using SWITCH as well.