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公开(公告)号:DE2245269A1
公开(公告)日:1973-05-10
申请号:DE2245269
申请日:1972-09-15
Applicant: IBM
Inventor: LLEWELYN ROGER JAMES , MINSHUL JAMES FRANCIS
IPC: G06F9/46 , G06F12/00 , G06F13/12 , G06F15/16 , G06F15/167 , G06F15/177 , G06F13/00
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公开(公告)号:DE3370090D1
公开(公告)日:1987-04-09
申请号:DE3370090
申请日:1983-06-30
Applicant: IBM
Inventor: HOLLOWAY BRIAN LEONARD , LLEWELYN ROGER JAMES
Abstract: A programmable timing circuit for a cathode ray tube includes a register stack (48) in which events to be timed are stored so that they are presented to comparators (45, 46 or 47) in the sequence in which they will occur. Each event is coded in terms of the position (character, line or row) on the screen at which it is to occur and flags stored with the values are decoded to identify the event being timed when a match is found between the presented value and the count in a character, line or row counter (40, 41 or 42) which is indicative of the current beam position on the screen. Values in the register stack can also control internal operations of the timing circuit, for example re-setting counters or re-addressing the stack.
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公开(公告)号:DE3578470D1
公开(公告)日:1990-08-02
申请号:DE3578470
申请日:1985-09-10
Applicant: IBM
Inventor: BEAVEN PAUL ANTHONY , HAWES ADRIAN JOHN , LLEWELYN ROGER JAMES
Abstract: A graphics display apparatus with a combined bit buffer and character graphics store includes a coded display buffer containing pointers to the store. The store is constituted by odd and even memories used to derive bit patterns for odd and even character cell columns on the display and is partitioned into a font area and a bit buffer area. In a first mode of operation, compatible with existing programmed symbol arrangements, pointers in the coded display buffer in conjunction with odd/even select signals and slice signals derive the bit patterns for each raster scan line of the display. In a second mode of operation, a graphic image to be displayed is stored as a bit map in the bit buffer area: the required bit pattern is derived using slice and odd/even select signals in conjunction with pointers stored in the coded display buffer.
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公开(公告)号:AU527208B2
公开(公告)日:1983-02-24
申请号:AU4990579
申请日:1979-08-14
Applicant: IBM
Inventor: HIRSCHMAN JOEL ALLEN , LLEWELYN ROGER JAMES , ROGERS ANTHONY HAYGARTH
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公开(公告)号:GB1218406A
公开(公告)日:1971-01-06
申请号:GB3207568
申请日:1968-07-04
Applicant: IBM
Inventor: GARDNER PETER ALAN EDWARD , HALLETT MICHAEL HENRY , TITMAN PETER JAMES , LLEWELYN ROGER JAMES
Abstract: 1,218,406. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 4 July, 1968, No. 32075/68. Heading G4A. An electronic data processing system includes two associative stores, data from one being used for an associative search in the other. General.-The system of Fig. 2 has three associative stores 21, 22, 23 each stored word having the fields shown. The local store 23 contains macro-instructions and operands, the working store 22 contains tables and the control store 21 contains sequences of micro-instructions for executing respective macro-instructions. In each store, matching may be done on the complete words or on portions indicated by the " mask " lines, and data read from or written into whole words or the portions not indicated by the respective mask lines. A match can set selectively a primary or a secondary trigger associated with the matched word, or a primary or secondary trigger associated with the next word. Reading and writing occurs with respect to that word or words having selectively either the primary trigger set or ther secondary trigger set, and if there is more than one such word the same data will be written into all such words (on writing) or the data read from the various words (on reading) will be ORed together. The set state of a primary or secondary trigger may be moved to the next such trigger for the same store, by a " next " operation. Each storage cell has three possible states 0, 1, X, the last being a " don't care " state which will match on either 0 or 1 indifferently. The macro-instructions are stored in consecutive locations in the local store, the first having a predetermined L.S. TAG field, successive macro-instructions being obtained by use of the " next " operation to step the set state of a primary trigger to the next primary trigger. The DATA 1 field of the macroinstruction is matched against the C.S. TAG fields of the control store to obtain the first micro-instruction, further micro-instructions being obtained by use of the " next " operation on the primary triggers of the store, similar to above. The L.S. TAG field of a micro-instruction can be matched against the L.S. TAG fields of the local store to obtain operands which are matched against the DATA 0 fields of the working store as the W.S. TAG of the microinstruction is matched against the W.S. TAG fields of the working store. The W.S. TAG applied specifies a stored table and the operands specify a word (or the first of a plurality of consecutive words) therein which contain the result of an operation on the operands (table look-up). The result can be transferred to the local store. The W.S. and L.S. TAGS matched against the working and local stores also control operation of the respective stores, and the control store is controlled by the C.S. OP field from itself. Micro-instruction subroutines can be sequenced through using the secondary triggers of the control store without disturbing the primary triggers used for sequencing through the main microprogramme in which the subroutine is embedded. Specifications 1,127,270 and 1,186,703 are referred to for the associative stores. Further details of table look-up.-Fig. 3 shows part of the working store for performing the AND, OR and EXCL-OR of two 4-bit operands A, B. The operands and a tag (which is 01, 11, 10 for AND, OR, EXCL-OR respectively) are matched against the corresponding " argument " fields shown in each word (row) the " output " fields of matching rows (there will be only one for AND, two for EXCL-OR and three for OR) being read out and ORed together. Shift and addition by table look-up are mentioned. Branch.-Micro-instruction branch is performed by obtaining the next micro-instruction by matching a 4-bit COND field from the working store and the C.S. TAG from the current micro-instruction (modified by ORing with the DATA 1 field from the working store, which will, however, usually be all zeros, or by the DATA 1 field from the local store) against the COND and C.S. TAG fields of the control store. The COND field from the working store indicates machine conditions, e.g. which of two operands is the larger, or overflow during addition. Macro-instruction branch is done similarly (in the local store) except that no COND field is involved. Modifications.-A conventional core store can be provided for holding the macro-instructions, its data input/output and address register both communicating with buses 27, 28 of Fig. 2. The core store is controlled by the W.S. TAGs from the control store (bus 24). An error (e.g. in an address) causes the core store to emit a C.S. TAG on bus 28 to cause entry into a diagnostic routine (no details). The local store holds instruction counts (for obtaining the next macro-instruction from the core store) which can be indexed by +1, +2, or -1 obtained from the working store, the indexing being by table look-up in the working store. The control store may be partly non-associative. Combination with second system.-The above system may be used as an interface between a transmission line and a larger data processing system, data from the line being buffered in the working store, then checked and edited before transfer to the larger system.
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公开(公告)号:DE3373233D1
公开(公告)日:1987-10-01
申请号:DE3373233
申请日:1983-09-28
Applicant: IBM
Inventor: CANTON DAVID ALFRED , HOLLOWAY BRIAN LEONARD , SARGEANT NICHOLAS BRIAN , LLEWELYN ROGER JAMES
Abstract: A data display apparatus employs a raster scan cathode ray tube (1), a character refresh buffer (2) and three character row buffers (5,6,15) to address a character generator (3) in conjunction with a slice counter (4) or offset slice counter (18) under control of an events control module (20). This enables data within a partition on the CRT to be scrolled smoothly (scan-line-by-scan-line) and characters of different height (requiring different numbers of scans) to be displayed on the same row of the CRT.
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公开(公告)号:DE2963416D1
公开(公告)日:1982-09-16
申请号:DE2963416
申请日:1979-08-21
Applicant: IBM
Inventor: HIRSCHMAN JOEL ALLEN , LLEWELYN ROGER JAMES , ROGERS ANTHONY HAYGARTH
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公开(公告)号:AU4990579A
公开(公告)日:1980-04-17
申请号:AU4990579
申请日:1979-08-14
Applicant: IBM
Inventor: HIRSCHMAN JOEL ALLEN , LLEWELYN ROGER JAMES , ROGERS ANTHONY HAYGARTH
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公开(公告)号:GB1218407A
公开(公告)日:1971-01-06
申请号:GB1759770
申请日:1968-07-04
Applicant: IBM
Inventor: GARDNER PETER ALAN EDWARD , HALLETT MICHAEL HENRY , TITMAN PETER JAMES , LLEWELYN ROGER JAMES
Abstract: 1,218,407. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 4 July, 1968, No. 17597/70. Divided out of 1,218,406. Heading G4A. In an electronic data processing system, logic and arithmetic functions are performed by table-look-up operations on stored function tables, there being a function store containing function tables, a work store arranged in operation to store operands, and a microprogramme store arranged in operation to emit micro-instructions each including an operation code, the function and work stores comprising respective decoders arranged to decode a part of the operation code particular to the store. The disclosure is essentially included in the parent.
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