公开(公告)号：GB2574957B

公开(公告)日：2020-08-19

申请号：GB201913461

申请日：2018-02-28

Applicant: IBM

Inventor： THOMAS PATRICK PARNELL ,  THOMAS MITTELHOLZER ,  TOBIAS BLAETTLER ,  CHARALAMPOS POZIDIS

IPC: H03M7/30 ,  G06F3/06 ,  G06N3/04 ,  G06N3/08 ,  H04N19/91

Abstract: A technique for non-binary context mixing in a compressor includes generating, by a plurality of context models, model predictions regarding a value of a next symbol to be encoded. A mixer generates a set of final predictions from the model predictions. An arithmetic encoder generates compressed data based on received input symbols and the set of final predictions. The received input symbols belong to an alphabet having a size greater than two and the mixer generates a feature matrix from the model predictions and trains a classifier that generates the set of final predictions.

公开(公告)号：GB2574957A

公开(公告)日：2019-12-25

申请号：GB201913461

申请日：2018-02-28

Applicant: IBM

Inventor： THOMAS PATRICK PARNELL ,  THOMAS MITTELHOLZER ,  TOBIAS BLAETTLER ,  CHARALAMPOS POZIDIS

IPC: G06N3/08 ,  H03M7/30 ,  H04N19/91

Abstract: A technique for non-binary context mixing in a compressor includes generating, by a plurality of context models, model predictions regarding a value of a next symbol to be encoded. A mixer generates a set of final predictions from the model predictions. An arithmetic encoder generates compressed data based on received input symbols and the set of final predictions. The received input symbols belong to an alphabet having a size greater than two and the mixer generates a feature matrix from the model predictions and trains a classifier that generates the set of final predictions.

公开(公告)号：GB2531783B

公开(公告)日：2016-09-28

申请号：GB201419352

申请日：2014-10-30

Applicant: IBM

Inventor： TOBIAS BLAETTLER ,  PETER MUELLER

IPC: H04L1/00 ,  H03M13/29

公开(公告)号：GB2531783A

公开(公告)日：2016-05-04

申请号：GB201419352

申请日：2014-10-30

Applicant: IBM

Inventor： TOBIAS BLAETTLER ,  PETER MUELLER

IPC: H04L1/00 ,  H03M13/29

Abstract: When decoding product coded data (typically row and column parity or equivalent codes 102,103) the invention identifies pathologic error patterns that have been detected but not corrected by the component codes. These are typically wherein multiple errors exist in a subset of the rows and columns (see Fig. 3 for instance). The method checks for zero remaining errors 104 which will terminate decoding and for error patterns that can be corrected by a further round of row/column decoding 105 which will trigger that further decoding. If neither of these cases occur the invention checks if too many errors exist 106 and if so decoding is terminated. If there are not too many errors the pathologic error pattern is deemed to be removable and the error bits are inverted/flipped 107 before initiating another round of row/column decoding. Checking whether an error pattern is removable is an optional feature in the claimed invention.

公开(公告)号：GB2531756A

公开(公告)日：2016-05-04

申请号：GB201419240

申请日：2014-10-29

Applicant: IBM

Inventor： TOBIAS BLAETTLER ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  MILOS STANISAVLJEVIC

IPC: G06F11/10

Abstract: A multi-chip device 100 for storing data comprises: a plurality of memory chips 10 adapted to store encoded input data 1, where each of the chips includes a detection unit adapted to perform a detection algorithm on the stored encoded input data for retrieving detected bits and to output the retrieved detected bits 3 and detection information 2 associated with the detection algorithm; an evaluation unit 20 adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit 30 adapted to receive the detected bits and to combine the detected bits; and a decoding unit 40 adapted to output decoded data by decoding the combined detected bits 5. The detection algorithm may be threshold based detection algorithm, such as a drift invariant detection algorithm. The device may facilitate improved bit error rates at the output of an error correction code engine, which may be particularly useful for non-volatile memory.