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    Updating corrective read voltage offsets in non-volatile random access memory
    2.
    发明专利
    Updating corrective read voltage offsets in non-volatile random access memory 未知

    公开(公告)号：GB2604517A

    公开(公告)日：2022-09-07

    申请号：GB202207336

    申请日：2020-10-16

    Applicant: IBM

    Inventor： NIKOLAOS PAPANDREOU ,  CHARALAMPOS POZIDIS ,  NIKOLAS IOANNOU ,  ROMAN PLETKA ,  RADU STOICA ,  SASA TOMIC ,  AARON FRY ,  TIMOTHY FISHER

    IPC: G06F11/07 ,  G06F11/10 ,  G11C16/26

    Abstract: A computer-implemented method, according to one approach, includes: using a first calibration scheme to calibrate the given page in the block by calculating a first number of independent read voltage offset values for the given page (606). An attempt is made to read the calibrated given page (608), and in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, a second calibration scheme is used to recalibrate the given page in the block (612). The second calibration scheme is configured to calculate a second number of independent read voltage offset values for the given page. An attempt to read the recalibrated given page is also made (614). In response to determining that an error correction code failure did occur when attempting to read the recalibrated given page, one or more instructions to relocate data stored in the given page are sent (618).

    Block mode toggling in data storage system
    3.
    发明专利
    Block mode toggling in data storage system 未知

    公开(公告)号：GB2599061A

    公开(公告)日：2022-03-23

    申请号：GB202200312

    申请日：2020-06-23

    Applicant: IBM

    Inventor： ROMAN ALEXANDER PLETKA ,  AARON DANIEL FRY ,  TIMOTHY FISHER ,  SASA TOMIC ,  NIKOLAOS PAPANDREOU ,  NIKOLAS IOANNOU ,  RADU IOAN STOICA ,  CHARALAMPOS POZIDIS ,  ANDREW WALLS

    IPC: G06F3/06

    Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a block switching metric for each block of memory in the storage system. A determination is made as to whether a first block in a first pool should be transferred to a second pool according to a block switching metric which corresponds to the first block. In response to determining that the first block in the first pool should be transferred to the second pool according to the block switching metric which corresponds to the first block, the first block is erased. The first block is then transferred from the first pool to a second RTU queue which corresponds to the second pool. A second block in the second pool is also erased and transferred from the second pool to a first RTU queue which corresponds to the first pool.

    Memory controllers for solid-state storage devices
    4.
    发明专利
    Memory controllers for solid-state storage devices 未知

    公开(公告)号：GB2606885B

    公开(公告)日：2023-10-11

    申请号：GB202208932

    申请日：2020-10-26

    Applicant: IBM

    Inventor： NIKOLAOS PAPANDREOU ,  ROMAN PLETKA ,  RADU STOICA ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  CHARALAMPOS POZIDIS

    IPC: G06F12/00 ,  G11C11/56

    Abstract: Aspects of the present invention disclose a method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.

    Adapting block pool sizes in a storage system
    5.
    发明专利
    Adapting block pool sizes in a storage system 未知

    公开(公告)号：GB2598878A

    公开(公告)日：2022-03-16

    申请号：GB202200305

    申请日：2020-06-23

    Applicant: IBM

    Inventor： ROMAN A PLETKA ,  RADU IOAN STOICA ,  SASA TOMIC ,  NIKOLAOS PAPANDREOU ,  NIKOLAS IOANNOU ,  AARON DANIEL FRY ,  TIMOTHY FISHER ,  CHARALAMPOS POZIDIS ,  ANDREW WALLS

    IPC: G06F3/06

    Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue. In response to determining that the number of blocks included in the first RTU queue is in the first range, a determination is made as to whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue. Moreover, in response to determining that the number of blocks included in the second RTU queue is not in the second range, valid data is relocated from one of the blocks in a first pool which corresponds to the first RTU queue. The block in the first pool is erased, and transferred from the first pool to the second RTU queue which corresponds to a second pool.

    Workload-adaptive data packing algorithm
    6.
    发明专利
    Workload-adaptive data packing algorithm 未知

    公开(公告)号：GB2554508B

    公开(公告)日：2019-01-16

    申请号：GB201711253

    申请日：2015-12-15

    Applicant: IBM

    Inventor： THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  CHARLES JOHN CAMP

    IPC: G06F11/10 ,  H03M13/13 ,  H03M13/15

    Abstract: A method, according to one embodiment, includes selecting, from a buffer, a combination of compressed logical pages of data to maximize an amount of used space in an error correction code container. The method also preferably includes processing the combination of compressed logical pages to generate error correction code data. Furthermore, the method may include writing the data corresponding to the combination of compressed logical pages and the associated error correction code data to a non-volatile random access memory. Other systems, methods, and computer program products are described in additional embodiments.

    Wear-aware block mode conversion in non-volatile memory
    8.
    发明专利
    Wear-aware block mode conversion in non-volatile memory 未知

    公开(公告)号：GB2599529A

    公开(公告)日：2022-04-06

    申请号：GB202117864

    申请日：2020-05-28

    Applicant: IBM

    Inventor： SASA TOMIC ,  ROMAN ALEXANDER PLETKA ,  NIKOLAS IOANNOU ,  NIKOLAOS PAPANDREOU ,  AARON DANIEL FRY ,  TIMOTHY FISHER ,  RADU IOAN STOICA

    IPC: G06F3/06

    Abstract: A non-volatile memory includes a plurality of physical blocks of storage each including a respective plurality of cells, where each of the plurality of cells is individually capable of storing multiple bits of data. A controller assigns physical blocks among the plurality of physical blocks to a first pool containing physical blocks operating in a first (e.g., QLC) mode for storing a greater number of bits per cell and assigns other physical blocks among the plurality of physical blocks to a second pool containing physical blocks operating in a second (e.g., SLC) mode for storing a lesser number of bits per cell. The controller transfers physical blocks between the first pool and the second pool based on at least bit error rates measured for the transferred physical blocks.

    Multi-chip device and method for storing data
    9.
    发明专利
    Multi-chip device and method for storing data 未知

    公开(公告)号：GB2531756A

    公开(公告)日：2016-05-04

    申请号：GB201419240

    申请日：2014-10-29

    Applicant: IBM

    Inventor： TOBIAS BLAETTLER ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  MILOS STANISAVLJEVIC

    IPC: G06F11/10

    Abstract: A multi-chip device 100 for storing data comprises: a plurality of memory chips 10 adapted to store encoded input data 1, where each of the chips includes a detection unit adapted to perform a detection algorithm on the stored encoded input data for retrieving detected bits and to output the retrieved detected bits 3 and detection information 2 associated with the detection algorithm; an evaluation unit 20 adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit 30 adapted to receive the detected bits and to combine the detected bits; and a decoding unit 40 adapted to output decoded data by decoding the combined detected bits 5. The detection algorithm may be threshold based detection algorithm, such as a drift invariant detection algorithm. The device may facilitate improved bit error rates at the output of an error correction code engine, which may be particularly useful for non-volatile memory.

    Memory controllers for solid-state storage devices
    10.
    发明专利
    Memory controllers for solid-state storage devices 未知

    公开(公告)号：GB2606885A

    公开(公告)日：2022-11-23

    申请号：GB202208932

    申请日：2020-10-26

    Applicant: IBM

    Inventor： NIKOLAOS PAPANDREOU ,  ROMAN PLETKA ,  RADU STOICA ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  CHARALAMPOS POZIDIS

    IPC: G06F12/00 ,  G11C11/56

    Abstract: A method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.

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