公开(公告)号：GB2531756A

公开(公告)日：2016-05-04

申请号：GB201419240

申请日：2014-10-29

Applicant: IBM

Inventor： TOBIAS BLAETTLER ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  MILOS STANISAVLJEVIC

IPC: G06F11/10

Abstract: A multi-chip device 100 for storing data comprises: a plurality of memory chips 10 adapted to store encoded input data 1, where each of the chips includes a detection unit adapted to perform a detection algorithm on the stored encoded input data for retrieving detected bits and to output the retrieved detected bits 3 and detection information 2 associated with the detection algorithm; an evaluation unit 20 adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit 30 adapted to receive the detected bits and to combine the detected bits; and a decoding unit 40 adapted to output decoded data by decoding the combined detected bits 5. The detection algorithm may be threshold based detection algorithm, such as a drift invariant detection algorithm. The device may facilitate improved bit error rates at the output of an error correction code engine, which may be particularly useful for non-volatile memory.

公开(公告)号：GB2556577A

公开(公告)日：2018-05-30

申请号：GB201801788

申请日：2016-12-09

Applicant: IBM

Inventor： ROMAN PLETKA ,  CHARLES JOHN CAMP ,  AARON DANIEL FRY ,  TIMOTHY JOHN FISHER ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  THOMAS PARNELL

IPC: G06F3/06 ,  G06F12/02 ,  G06F11/10

Abstract: A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT)data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physica1 blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.

公开(公告)号：GB2554508B

公开(公告)日：2019-01-16

申请号：GB201711253

申请日：2015-12-15

Applicant: IBM

Inventor： THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  CHARLES JOHN CAMP

IPC: G06F11/10 ,  H03M13/13 ,  H03M13/15

Abstract: A method, according to one embodiment, includes selecting, from a buffer, a combination of compressed logical pages of data to maximize an amount of used space in an error correction code container. The method also preferably includes processing the combination of compressed logical pages to generate error correction code data. Furthermore, the method may include writing the data corresponding to the combination of compressed logical pages and the associated error correction code data to a non-volatile random access memory. Other systems, methods, and computer program products are described in additional embodiments.

公开(公告)号：GB2556577B

公开(公告)日：2019-01-09

申请号：GB201801788

申请日：2016-12-09

Applicant: IBM

Inventor： ROMAN PLETKA ,  CHARLES JOHN CAMP ,  AARON DANIEL FRY ,  TIMOTHY JOHN FISHER ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  THOMAS PARNELL

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/10

Abstract: A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physical blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.

公开(公告)号：GB2554508A

公开(公告)日：2018-04-04

申请号：GB201711253

申请日：2015-12-15

Applicant: IBM

Inventor： THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  CHARLES JOHN CAMP

IPC: G06F11/10 ,  H03M13/13 ,  H03M13/15

Abstract: A method, according to one embodiment, includes selecting, from a buffer, a combination of compressed logical pages of data to maximize an amount of used space in an error correction code container. The method also preferably includes processing the combination of compressed logical pages to generate error correction code data. Furthermore, the method may include writing the data corresponding to the combination of compressed logical pages and the associated error correction code data to a non-volatile random access memory. Other systems, methods, and computer program products are described in additional embodiments.

公开(公告)号：GB2525430B

公开(公告)日：2016-07-13

申请号：GB201407279

申请日：2014-04-25

Applicant: IBM

Inventor： THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  THOMAS PARNELL ,  CHARALAMPOS POZIDIS

IPC: H04L1/00 ,  G06F11/10 ,  H03M13/03