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公开(公告)号：DE2000565A1
公开(公告)日：1970-07-23
申请号：DE2000565
申请日：1970-01-07
Applicant: IBM
Inventor： CRAIG BOSSEN DOUGLAS , HSIAO MU-YUE , FAIRBANKS SELLERS JUN FREDERIC , TIENWEN CHIEN ROBERT
Abstract: 1,247,823. Error-correcting systems. INTERNATIONAL BUSINESS MACHINES CORP., and ROBERT TIENWEN CHIEN. 8 Jan., 1970 [8 Jan., 1969], No. 1041/70. Heading G4A. A message containing k data bits has 2m check bits added to it (k#m 2 , where m=integer greater than 1) for each of t error-correcting capabilities (t#1), and a decoder comprises t parity-checking circuits supplying outputs to an error-correcting circuit for that bit. As an example, where k=25 and m=5, the message bits d 0 -d 24 are considered arranged as a 5 x 5 matrix, check bits c 1 -c 5 are derived by exclusive OR operation on the matrix rows (e.g. c 1 =EXOR (do, d 1 , d 2 , d 3 , d 4 ) and check bits c 6 -c 10 are similarly derived from the matrix columns (e.g. c 6 =EXOR d 0 , d 5 , d 10 , d 15 , d 20 ) to provide for single error correction. For each additional error correction capability, a pair of orthogonal Latin squares such as L 1 , L 2 and L 3 , L 4 , Fig. 4, is used to select two groups of 5 bits from the matrix, each group comprising bits located in positions marked with the same number in the Latin squares, the additional check bits c 11 -c 15 (L 1 ), C 16 -C 20 (L 2 ) again being derived by exclusive OR operation on the 5 selected bits. Each bit d 0 -d 24 therefore occurs in only two of the equations defining each set of mt check bits. For each bit, such as d 0 , the error-correcting decoder comprises a module I-III, Fig. 5, for each error-correcting capability, each module consisting of a pair of exclusive OR circuits such as 30, 32 receiving inputs corresponding to the check bit equations in which that bit occurs, e.g. for do circuit 30 has inputs d 1 -d 4 and c 1 . Each circuit 30, 32 provides an output which should be a copy of the corresponding bit, and these copies, together with the original bit are supplied to a majority logic gate 38 to provide a corrected output, assuming not more than the number of random errors allowed for have occurred. For the ease where k
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公开(公告)号：DE1287339B
公开(公告)日：1969-01-16
申请号：DEJ0027831
申请日：1965-04-03
Applicant: IBM
Inventor： FAIRBANKS SELLERS JUN FREDERIC , HOPEWELL JUNCTION , TRENT BROWN DAVID
Abstract: 1,053,174. Error detection and correction. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 9, 1965 [April 6, 1964 (3)], No. 9873/65. Heading G4C. The position of an erroneous bit in an incorrect byte in a group of bytes is detected with the aid of redundancy in each byte and a cyclic redundancy check byte provided for the group of bytes, two byte indications being placed in respective cyclic shift registers and one shifted until a comparison indicates equality, the number of shifts indicating the said position. Data is recorded on magnetic tape as a block of data bytes followed by a cyclic redundancy check (CRC) byte and a longitudinal redundancy check (LRC) byte. Each data byte has internal redundancy (a parity bit, or the number of ONE bits is always the same). The LRC byte provides a parity bit for each track of the tape (i.e. corresponding bit positions in all the other bytes). The mathematical theory of the cyclic checking (CRC) is given in the Specification. During writing on the tape, as the data bytes are sent to the tape, they are also sent to a feedback-connected CRC shift register (CRCR) where each byte is EX-ORed with the present contents of the register and the result shifted one position. When the last data byte has been received, the contents of the CRC register are given one extra shift and then with certain bits complemented, are passed to the tape via a read-write (R/W) register as the CRC byte. Then the LRC byte is recorded on the tape. The bytes are read again concurrently with the writing operation, and vertical redundancy checks (VRC, the internal redundancy of each byte) and LRC performed. During reading from the tape, the bytes are transferred via the R/W register to the CRCR (except the LRC byte) and a VRC is performed on each byte. In detection of a VRC error, a ONE is entered in a feedback-connected error pattern register (EPR) which is being shifted in synchronism with the CRCR. If a CRC, VRC or LRC error has occurred during reading, the tape is backspaced and the track in error determined as follows. The contents of the EPR are transferred to the R/W register (previously cleared) and a ONE inserted in the top position of the EPR (otherwise clear). The EPR and CRCR are shifted together until the contents of the CRCR equal those of the R/W register, as determined by an all ZEROES output from EX-OR gates 16 (Fig. 2, not shown). The position of the ONE bit in the EPR then gives the track in error, and the CRCR is reset. A second reading of the tape commences and on detection of a VRC error in a byte, the contents of the EPR are supplied to the EX-OR gates 16 (not shown) through which the tape byte is passing to complement the bit which is in the erroneous channel. The bytes, after correction, are sent to the CRCR. When all the bytes have been received, the CRCR is sampled for a CRC error. Also, an LRC register (LRCR) which received the uncorrected bytes is sampled for an LRC error, positions in which an error correction took place being ignored for this purpose. Backwards read may be performed by reversing directions of shift or having reversible input connections.
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公开(公告)号：DE1449802A1
公开(公告)日：1968-12-05
申请号：DE1449802
申请日：1964-12-23
Applicant: IBM
Inventor： TRENT BROWN DAVID , FAIRBANKS SELLERS JUN FREDERIC
IPC: G11B20/14
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