公开(公告)号：DE3777810D1

公开(公告)日：1992-04-30

申请号：DE3777810

申请日：1987-12-15

Applicant: IBM

Inventor： TRYNOSKY STEPHEN WAYNE ,  PARSONS JR

IPC: G06F3/153 ,  G09G1/00 ,  G09G1/16 ,  G09G5/22 ,  G09G5/24

Abstract: A raster scan display system uses a RAM character generator and a dual port video buffer random access memory. The dual port buffer has a shift register output for holding a row of data from the random access memory. The buffer has two partitions, one containing, at consecutive locations, character data and attribute data, the other, character data and font data. In a first mode of operation using the first partition, data transferred to the shift register comprises character data to address the character generator store and attribute data for combination with font data retrieved from the character generator store to provide video data. In a second mode, using the second partition, character and font data transferred to the shift register is used to address and update the character generator store.

公开(公告)号：GB2202720B

公开(公告)日：1991-04-17

申请号：GB8728926

申请日：1987-12-10

Applicant: IBM

Inventor： TRYNOSKY STEPHEN WAYNE ,  PARSONS JR DONALD HOLCOMBE

IPC: G06F3/153 ,  G09G1/00 ,  G09G1/16 ,  G09G5/22 ,  G09G5/24

Abstract: A raster scan display system uses a RAM character generator and a dual port video buffer random access memory. The dual port buffer has a shift register output for holding a row of data from the random access memory. The buffer has two partitions, one containing, at consecutive locations, character data and attribute data, the other, character data and font data. In a first mode of operation using the first partition, data transferred to the shift register comprises character data to address the character generator store and attribute data for combination with font data retrieved from the character generator store to provide video data. In a second mode, using the second partition, character and font data transferred to the shift register is used to address and update the character generator store.

公开(公告)号：AT49315T

公开(公告)日：1990-01-15

申请号：AT84107799

申请日：1984-07-05

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  SAENZ JESUS ANDRES ,  TRYNOSKY STEPHEN WAYNE

IPC: G09G5/00 ,  G06F3/00 ,  G06F3/14 ,  G06F7/02 ,  G06T7/00 ,  G09G1/16 ,  G09G5/02 ,  G09G5/393 ,  G09G5/395 ,  G06F15/70

Abstract: In a bit mapped raster scan digital display system, a number of maps (MAPO-MAP3), each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares each bit of the two bytes of data with the correspondingly positioned bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system, the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.

公开(公告)号：BE1001069A3

公开(公告)日：1989-06-27

申请号：BE8800017

申请日：1988-01-08

Applicant: IBM

Inventor： TRYNOSKY STEPHEN WAYNE ,  PARSONS DONALD HOLCOMBE JR

IPC: G06F3/153 ,  G09G1/00 ,  G09G1/16 ,  G09G5/22 ,  G09G5/24 ,  G09G

Abstract: Système d'affichage à balayage de trame utilisant un générateur de caractères à mémoire RAM et une mémoire à accès aléatoire de mémoire intermédiaire vidéo à ports doubles, la mémoire intermédiaire vidéo à ports doubles recevant une sortie de registre à décalage pour retenir une rangée de données depuis la mémoire à accès aléatoire, la mémoire intermédiaire ayant deux parties, l'une contenant dans des emplacements consécutifs des données de caractère et des données d'attribut et l'autre contenant des données de caractère et des données de type caractère.

公开(公告)号：GB2202720A

公开(公告)日：1988-09-28

申请号：GB8728926

申请日：1987-12-10

Applicant: IBM

Inventor： TRYNOSKY STEPHEN WAYNE ,  PARSONS JR DONALD HOLCOMBE

IPC: G06F3/153 ,  G09G1/00 ,  G09G1/16 ,  G09G5/22 ,  G09G5/24 ,  G09G1/02

Abstract: A raster scan display system uses a RAM character generator and a dual port video buffer random access memory. The dual port buffer has a shift register output for holding a row of data from the random access memory. The buffer has two partitions, one containing, at consecutive locations, character data and attribute data, the other, character data and font data. In a first mode of operation using the first partition, data transferred to the shift register comprises character data to address the character generator store and attribute data for combination with font data retrieved from the character generator store to provide video data. In a second mode, using the second partition, character and font data transferred to the shift register is used to address and update the character generator store.

公开(公告)号：AU566038B2

公开(公告)日：1987-10-08

申请号：AU3137484

申请日：1984-08-01

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  SAENZ JESUS ANDRES ,  TRYNOSKY STEPHEN WAYNE

IPC: G09G5/00 ,  G09G5/34 ,  G09G5/395 ,  G06F3/153

Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.

公开(公告)号：BR8404080A

公开(公告)日：1985-07-16

申请号：BR8404080

申请日：1984-08-15

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  SAENZ JESUS ANDRES ,  TRYNOSKY STEPHEN WAYNE

IPC: G09G5/00 ,  G09G5/34 ,  G09G5/395 ,  G06F3/00 ,  G06F15/64

Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.

公开(公告)号：HK61692A

公开(公告)日：1992-08-28

申请号：HK61692

申请日：1992-08-20

Applicant: IBM

Inventor： MOREL JEANNE ELLEN ,  RACKLEY DARWIN PRESTON ,  TRYNOSKY STEPHEN WAYNE ,  WALL WILLIAM ALLAN

IPC: G09G1/16 ,  G09G5/00 ,  G09G1/28 ,  G09G5/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/391 ,  G06F15/62

Abstract: An all points addressable raster scan graphics display system is operable in two modes. In the first mode, data is extracted from a refresh store, serialised, modified, and applied to a display device at a first frequency. In the second mode, data is extracted from the refresh store, serialised and partially modified at said first frequency, but it is then further modified and passed to the display device at an even sub harmonic, for example half, of the first frequency. The further modification includes concatenation of successive groups of display data bits. Accordingly, with the raster scan device operating at a constant scan velocity, the first mode provides a high picture element definition but relatively low colour definition display, and the second mode provides a display with an even submultiple, for example half, the picture element definition but considerably greater colour definition.

公开(公告)号：IT1217360B

公开(公告)日：1990-03-22

申请号：IT1994788

申请日：1988-03-25

Applicant: IBM

Inventor： TRYNOSKY STEPHEN WAYNE ,  DONALD HOLCOMBE PARSONS JR

IPC: G06F3/153 ,  G09G1/00 ,  G09G1/16 ,  G09G5/22 ,  G09G5/24 ,  G06K

Abstract: A raster scan display system uses a RAM character generator and a dual port video buffer random access memory. The dual port buffer has a shift register output for holding a row of data from the random access memory. The buffer has two partitions, one containing, at consecutive locations, character data and attribute data, the other, character data and font data. In a first mode of operation using the first partition, data transferred to the shift register comprises character data to address the character generator store and attribute data for combination with font data retrieved from the character generator store to provide video data. In a second mode, using the second partition, character and font data transferred to the shift register is used to address and update the character generator store.

公开(公告)号：MX157249A

公开(公告)日：1988-11-08

申请号：MX20231684

申请日：1984-08-09

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  SAENZ JESUS ANDRES ,  TRYNOSKY STEPHEN WAYNE

IPC: G09G5/00 ,  G09G5/34 ,  G09G5/395 ,  G09G1/02 ,  G09G1/14

Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.