公开(公告)号：DE2962031D1

公开(公告)日：1982-03-11

申请号：DE2962031

申请日：1979-04-26

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  GAUR SANTOSH PRASAD ,  POGGE HANS BERNHARD

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/08 ,  H01L29/735 ,  H01L27/08 ,  H01L29/72

Abstract: Lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region are described. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages.

公开(公告)号：DE2861136D1

公开(公告)日：1981-12-17

申请号：DE2861136

申请日：1978-09-06

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/70 ,  H01L23/48

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

公开(公告)号：AU3844878A

公开(公告)日：1980-01-31

申请号：AU3844878

申请日：1978-07-28

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/82 ,  H01L27/04 ,  H01L29/72 ,  H01L21/20 ,  H01L21/22 ,  H01L21/265 ,  H01L21/285 ,  H01L21/306 ,  H01L21/31

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

公开(公告)号：DE3065767D1

公开(公告)日：1984-01-05

申请号：DE3065767

申请日：1980-07-10

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  CAVALIERE JOSEPH RICHARD ,  KONIAN RICHARD ROBERT ,  SRINIVASAN GURUMAKONDA ,  STOLLER HERBERT IVAN ,  WALSH JAMES LEO

IPC: H01L21/033 ,  H01L29/08 ,  H01L29/10 ,  H01L21/00

Abstract: A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.

公开(公告)号：DE3160804D1

公开(公告)日：1983-10-06

申请号：DE3160804

申请日：1981-02-25

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/329 ,  H01L29/47 ,  H01L29/872 ,  H01L21/60 ,  H01L21/31 ,  H01L29/48 ,  H01L29/91

公开(公告)号：DE2854009A1

公开(公告)日：1979-07-12

申请号：DE2854009

申请日：1978-12-14

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  CASES MOISES ,  CHANG FUNG YUEL

IPC: G11C11/56 ,  G11C19/28 ,  G11C27/04 ,  H01L27/10 ,  H01L27/105 ,  H03H11/26 ,  G11C7/00 ,  G11C11/24

公开(公告)号：DE3279917D1

公开(公告)日：1989-10-05

申请号：DE3279917

申请日：1982-06-15

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  MAUER IV JOHN LESTER ,  SARKARY HOMI GUSTADJI

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/306

Abstract: The method comprises blanket depositing a layer of a first material on a semiconductor structure, on the surface of which protruding regions (34A) have been formed bordering with a vertical wall (40) on adjacent areas, and subsequently removing completely or selectively that layer by reactive ion etching where prior to the deposition of said layer the vertical wall (40) is reshaped either by removing material from that wall (40) or by accumulating a second material on said wall (40). The method prevents that uncontrolled residues of materials like a doped polysilicon after reactive ion etching steps. These residues might be detrimental to devices and elements, like transistors and resistors formed in the semi-conductor substrate.

公开(公告)号：DE3072023D1

公开(公告)日：1987-10-08

申请号：DE3072023

申请日：1980-12-12

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  SRINIVASAN GURUMAKONDA RAMASWA

IPC: H01L21/20 ,  H01L21/268 ,  H01L21/312 ,  H01L21/331 ,  H01L21/762 ,  H01L29/04 ,  H01L29/73

Abstract: The method starts from a monocrystalline semiconductor substrate (2) having a highly doped region (1), and being covered by an oxide mask (3) which is apertured above region (1). A layer (6) of polysilicon is deposited over oxide mask (3). The structure is exposed to laser radiation (14) to convert layer (6) into monocrystalline silicon within and above the oxide apertures. The method is useful in making filamentary pedestal transistors without extrinsic base-collector junctions. In this present case, region (1) serves as a subcollector, two polycrystalline areas are made monocrystalline, with the one area(4) and the polycrystalline area (7) surrounding it being doped with a base dopant, and the other area (5) being made the collector reach-through region. The upper portion (10) of area (4) is made the emitter.

公开(公告)号：DE3070658D1

公开(公告)日：1985-06-20

申请号：DE3070658

申请日：1980-12-12

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L23/532 ,  H01L21/00 ,  H01L21/314

Abstract: A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite conductivity epitaxial layer and substrate. Multiple layered mass of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

公开(公告)号：DE2657511A1

公开(公告)日：1977-07-07

申请号：DE2657511

申请日：1976-12-18

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  ANANTHA NARASIPUR GUNDAPPA ,  DOCKERTY ROBERT CHARLES

IPC: H01L21/8247 ,  G11C11/36 ,  G11C16/04 ,  H01L27/07 ,  H01L27/102 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L29/872 ,  H01L29/94 ,  G11C11/34

Abstract: 1503300 Semiconductor memory device INTERNATIONAL BUSINESS MACHINES CORP 16 Nov 1976 [31 Dec 1975] 47660/76 Heading H1K A semiconductor memory device comprises an electrode 18, Fig. 2, forming a Schottkybarrier contact with an epitaxial layer 13 of one conductivity type, the electrode overlying a region 14 of second conductivity type formed in a surface region of a substrate 11 of said one conductivity type, and an insulating layer 21, 22 around the Schottky-barrier contact overlain by a conductive layer 24 which is insulated from the said electrode, the arrangement being such that when a predetermined voltage is applied across the Schottky barrier, the electrons produced in the avalanche breakdown of the Schottky diode are trapped in the insulating layer. During the above mentioned write operation, the conductive layer 24, typically of doped polysilicon is held at a high positive potential as compared to the electrode 18 and the terminals 30, 33 are at zero potential. During a non-destructive read operation, a substantial current flows from the electrode 18 to the P + diffusion 14 because of the trapped charges forming a depletion region 45 in the epitaxial layer. The insulating layer typically comprises silicon oxide and silicon nitride sublayers and the polysilicon layer 24 is separated from the electrode 18 by a silicon dioxide layer 26. Electrical connection to the P+ region 14 is achieved through a P+ diffused zone and a metal electrode (not shown), whereas the electrical contact 33 is made either at the bottom of the substrate or at the top of the epitaxial layer through an N + diffused region. A member matrix comprising the memory devices formed at the cross-overs of metallized tracks (31a, 31b), and the P+ diffused zones (14a, 14b), Fig. 1 (not shown) is disclosed