公开(公告)号：JPH08111789A

公开(公告)日：1996-04-30

申请号：JP23271994

申请日：1994-09-28

Applicant: IBM

Inventor： TSUJIMOTO HIROYUKI ,  HAYATA MASAYUKI ,  NISHIMURA KOICHI

IPC: H04N5/06 ,  H03L7/10 ,  H04L7/033 ,  H04N5/04 ,  H04N5/10 ,  H04N5/12

Abstract: PURPOSE: To perform conversion to signals for stabilizing a processing in a PLL at all times even when the different kinds of composite synchronizing signals are inputted. CONSTITUTION: In a horizontal synchronization gate signal generation circuit 34, corresponding to characteristics inside a vertical synchronizing signal area, horizontal synchronization gate signals SHG for which a prescribed margin is added to the front and back of pulse signals obtained by the composite synchronizing signals CSH, cycle data and pulse width data, etc., are generated or the horizontal synchronization gate signals SHG for which the margin on a front side is canceled are generated inside the vertical synchronizing signal area recognized by vertical gate signals SVG. The horizontal synchronization gate signals SHG generated in such a manner are inputted to the second input terminal of an AND circuit 30 and ANDed with the composite synchronizing signals CSH inputted to a first input terminal and thus, horizontal synchronizing signals are surely obtained even inside the vertical synchronizing signal area.