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公开(公告)号:JPH0898055A
公开(公告)日:1996-04-12
申请号:JP22783894
申请日:1994-09-22
Applicant: IBM
Inventor: NISHINO HIROZO , NISHIMURA KOICHI , HAYATA MASAYUKI
Abstract: PURPOSE: To avoid errors due to jitters, delays or the like in separating and taking out synchronizing signals from image signals to which synchronizing signals are added. CONSTITUTION: Sync-on-green signals are taken out from a branch line 56 branched on the way of a signal line 54 which connects an output terminal of a video amplifier 36 to an A/D converter 42, and are connected to an input terminal on the positive side of a comparator 58. It means that a voltage that is amplified by the video amplifier 36 and corresponds to luminance signal shifted by an offset voltage is inputted in an input terminal on the positive side of the comparator 58. On the other hand, to an input terminal on the negative side of the comparator 58 is inputted a threshold voltage for detecting falls of the above-mentioned synchronous signals. When a voltage corresponding to image signals becomes lower than the threshold voltage, the comparator 58 judges that synchronizing signals are detected and outputs a low level (L) signal.
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公开(公告)号:JP2000251544A
公开(公告)日:2000-09-14
申请号:JP4764399
申请日:1999-02-25
Applicant: IBM
Inventor: ISHII SHIGERU , MORI SHIGEKI , NISHIMURA KOICHI , NAKAI SHINJI
Abstract: PROBLEM TO BE SOLVED: To release heat generated in a wearable computer or the like using a cable. SOLUTION: Heat generated by a CPU 30 in a PC body 3 is transferred to a heat collecting member 38, and then is transferred to a heat conductive sheet 22 of a cable 2 through a heat pipe 32 and a connecting member 34. The heat conductive sheet 22 guides the heat transferred through the heat collecting member 38, the heat pipe 32, and the connecting member 34 to the longitudinal direction of the cable 2, and simultaneously gradually releases it to the outside through a coating to radiate heat in the PC body 3.
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公开(公告)号:JPH08111789A
公开(公告)日:1996-04-30
申请号:JP23271994
申请日:1994-09-28
Applicant: IBM
Inventor: TSUJIMOTO HIROYUKI , HAYATA MASAYUKI , NISHIMURA KOICHI
Abstract: PURPOSE: To perform conversion to signals for stabilizing a processing in a PLL at all times even when the different kinds of composite synchronizing signals are inputted. CONSTITUTION: In a horizontal synchronization gate signal generation circuit 34, corresponding to characteristics inside a vertical synchronizing signal area, horizontal synchronization gate signals SHG for which a prescribed margin is added to the front and back of pulse signals obtained by the composite synchronizing signals CSH, cycle data and pulse width data, etc., are generated or the horizontal synchronization gate signals SHG for which the margin on a front side is canceled are generated inside the vertical synchronizing signal area recognized by vertical gate signals SVG. The horizontal synchronization gate signals SHG generated in such a manner are inputted to the second input terminal of an AND circuit 30 and ANDed with the composite synchronizing signals CSH inputted to a first input terminal and thus, horizontal synchronizing signals are surely obtained even inside the vertical synchronizing signal area.
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